A Noise-Canceling Charge Pump for Area Efficient PLL Design

Urakawa, Go; Kobayashi, Hiroyuki; Deguchi, Jun; Fujimoto, Ryuichi

doi:10.1109/rfit49453.2020.9226191

Cited by 3 publications

(1 citation statement)

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“…Compared with conventional spiral inductor with the same inductance and Q-value, the occupied area of the proposed inductor (Area=X*Y) is reduced by 28.7% at the moderate Q-value of 9.4, which is enough for the target clock jitter. In addition, a noise-cancelling charge pump [21] is also implemented in the PLL.…”

Section: Transceiver Architecturementioning

confidence: 99%

A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver

TACHIBANA,

CU NGO,

URAKAWA

et al. 2024

IEICE Trans. Fundamentals

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Although baud-rate clock and data recovery (CDR) such as Mueller-Müller (MM) CDR is adopted to ADC-based receivers (RXs), it suffers from false-lock points when the RXs handle PAM4 data pattern because of the absence of edge data. In this paper, a false-lock-aware locking scheme is proposed to address this issue. After the false-lock-aware locking scheme, a clock phase is adjusted to achieve maximum eye height by using a post-1-tap parameter for an FFE in the CDR loop. The proposed techniques are implemented in a 56-Gb/s PAM4 transceiver. A PLL uses an area-efficient "glasses-shaped" inductor. The RX comprises an AFE, a 28-GS/s 7-bit time-interleaved SAR ADC, and a DSP with a 31-tap FFE and a 1-tap DFE. A TX is based on a 7-bit DAC with a 4-tap FFE. The transceiver is fabricated in 16-nm CMOS FinFET technology, and achieves a BER of less than 1e-7 with a 30-dB loss channel. The measurement results show that the MM CDR escapes from false-lock points, and converges to near the optimum point for large eye height.

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Section: Transceiver Architecturementioning

confidence: 99%