A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

Glittas, Antony Xavier; Sellathurai, Mathini; Lakshminarayanan, G.

doi:10.1109/tvlsi.2015.2504391

Cited by 41 publications

(25 citation statements)

References 11 publications

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“…The design was synthesized on Xilinx Vertex-5 FPGA with XC5VLX110T device, FF1136 package, -1 speed with a word length of 8 bits.The corresponding simulation results of area, delay and power for different FFTsizes (N)are shown in Table 1, Table 2 and Table 3. The simulation results of proposed KD FFT are compared with those of RD FFT and FFT in [7]. Here, KD FFT means FFT with KS adders and Dadda multipliers.…”

Section: Resultsmentioning

confidence: 99%

“…Here, KD FFT means FFT with KS adders and Dadda multipliers. RD FFT means FFT with RC adders and Dadda multipliers whereas FFT in [7] uses RC adders and array multipliers. From the simulation results of area, observe that the proposed KD FFT uses less number of look-up tables (LUTs) and less occupied slices compared to that of the other two FFT architectures.…”

Section: Resultsmentioning

confidence: 99%

“…A radix-2 pipelined MDC FFT architecture [7] is designed to process two independent data streams concurrently with its outputs in normal order. To generate normal output order, the processor does not use any additional bit reversal circuits.…”

Section: Radix-2 MDC Fft Architecture To Process Two Data Streamsmentioning

confidence: 99%

“…The Dadda multiplier is a fast tree multiplier which requires less half adders and full adders in its architecture. In this paper, the performance of the proposed FFT architecture, which uses the KS adder and Dadda multipliers, is compared with the performance of FFT, which uses Ripple Carry (RC) adders and Dadda multipliers, and also with the performance of the FFT architecture [7] which uses RC adders and array multipliers. The operations of KS adder and Dadda multiplier are discussed in sub sections.…”

Section: Performance Efficient Fft With Ks Adders and Dadda Multmentioning

confidence: 99%

“…There exists a combined SDC-SDF FFT which gives normal order output but its throughput is low. In [7], a new FFT architecture is proposed for processing two data streams in normal input-output order. Its speed more compared to previous FFT processors.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Performance Efficient MDC Based Pipelined FFT Processor for Mimo - Ofdm

2017

IJAERD

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Radix-2 MDC Fft Architecture To Process Two Data Streamsmentioning

confidence: 99%

Section: Performance Efficient Fft With Ks Adders and Dadda Multmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Performance Efficient MDC Based Pipelined FFT Processor for Mimo - Ofdm

2017

IJAERD

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Area–time–energy efficient architecture of CBNS‐based fast Fourier transform

Das,

Harshavardhan Reddy,

Mandal

et al. 2024

Circuit Theory & Apps

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A new approach for implementing the fast Fourier transform (FFT) using complex binary number system (CBNS) is presented in this paper. The advantage of using CBNS is that instead of processing the real and imaginary parts of a complex number separately, we can process both as a single entity. A total of four FFT architectures have been developed, which are 16‐, 64‐, 256‐, and 1024‐point FFT architectures. The proposed FFT is designed using Verilog‐HDL and implemented using a Virtex‐7 field‐programmable gate array (FPGA). The maximum clock rate achieved by the proposed FPGA‐based design is 376.1 MHz. The FPGA resource utilization of the FFT is less than the state‐of‐the‐art FFT designs. An application‐specific integrated circuit (ASIC) for the FFT is also designed. The normalized energy per FFT of the proposed ASIC is 0.14 nJ, and the normalized area per FFT of the ASIC is 1.08 mm2 which is less than other existing designs.

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Design of High‐Performance Radix‐Power‐of‐2 Butterfly Architectures for FFT Implementation by Cosine Coefficients Extraction

Moni Varghese,

Sundaram

2024

Circuit Theory & Apps

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Designing FFTs with higher radix butterfly units are increasingly in demand to combat the high throughput of 20 Gbps of the current 5G and 1 Tbps for beyond 5G technologies. Previous higher radix FFTs were implemented in FPGA, giving importance to area and power. This paper presents the design of radix‐power‐of‐2 butterfly circuit, using the proposed radix cosine coefficients' extractor equation that is applicable to all the inputs. This enables efficient pipelined shift‐add implementation of the required complex rotations. The proposed methodology encompasses the implementation of any power‐of‐two‐radix butterfly to realize large size FFT, essential for real‐time 5G and 6G applications. The proposed radix‐4, radix‐8, radix‐16, and radix‐32 architectures are implemented and verified on Xilinx Spartan‐7 FPGA using Vivado Design Suite (v2018). The results demonstrate that the proposed radix‐16 and radix‐32 architectures achieve a higher clock frequency, by a factor of 5.23 and 6.76, respectively, compared to the most recent literature. For performance analysis, the area‐delay and power‐delay products of the proposed radix‐16 and radix‐32 butterfly architecture are computed. The proposed radix‐16 butterfly architecture exhibits a 13.3% reduction in area‐delay product and a 34.25% decrease in power‐delay product compared to recent literatures. Similarly, the radix‐32 architecture shows a 27.31% lower area‐delay product and a 0.63% lower power‐delay product.

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A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

Cited by 41 publications

References 11 publications

Performance Efficient MDC Based Pipelined FFT Processor for Mimo - Ofdm

Performance Efficient MDC Based Pipelined FFT Processor for Mimo - Ofdm

Area–time–energy efficient architecture of CBNS‐based fast Fourier transform

Design of High‐Performance Radix‐Power‐of‐2 Butterfly Architectures for FFT Implementation by Cosine Coefficients Extraction

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