A notched metal gate MOSFET for sub-0.1 μm operation

Pidin, S.; Mushiga, M.; Shido, H.; Yamamoto, Takeshi; Sambonsugi, Y.; Tamura, Y.; Sugii, T.

doi:10.1109/iedm.2000.904405

Cited by 3 publications

(3 citation statements)

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“…1b͒, so as to control the Miller capacitance ͑gate-to-drain capacitance͒ and enhance the high frequency performance of the transistors. [2][3][4][5] Methods of formation of a notched gate by selective plasma ͑dry͒ or wet underetch of bilayered gate electrodes on SiO 2 have been demonstrated. 3,4 In the meantime, metal gate and dielectrics of high relative dielectric constant ͑high-͒ are expected to replace the traditional poly-Si and SiO 2 gate stack to reduce the EOT while maintaining acceptable low gate leakage current through the gate dielectrics.…”

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confidence: 99%

“…[2][3][4][5] Methods of formation of a notched gate by selective plasma ͑dry͒ or wet underetch of bilayered gate electrodes on SiO 2 have been demonstrated. 3,4 In the meantime, metal gate and dielectrics of high relative dielectric constant ͑high-͒ are expected to replace the traditional poly-Si and SiO 2 gate stack to reduce the EOT while maintaining acceptable low gate leakage current through the gate dielectrics. 1,6 In this article, we demonstrate the formation of notched-gate pMOSFET with an atomic layer deposition ͑ALD͒ TiN metal gate and an ALD Al 2 O 3 /HfO 2 /Al 2 O 3 high-nanolaminate gate dielectric.…”

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Notched-Gate pMOSFET with ALD TiN/High-κ Gate Stack Formed by Selective Wet Etching

Hellström

Östling

et al. 2004

Electrochem. Solid-State Lett.

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Proof-of-concept notched-gate metal-oxide-semiconductor field-effect transistor ͑MOSFET͒ with the integration of atomic layer deposition ͑ALD͒ metal gate/high-dielectric is demonstrated. The notched gate is formed by a combination of plasma dry etch and subsequent selective wet etch of a poly-Si 0.7 Ge 0.3 /TiN bilayer gate electrode stack. The height of the notch is determined mainly by the thickness of the TiN layer, and the width is controlled by the wet underetch of the TiN beneath the Si 0.7 Ge 0.3 layer. Compared with reference MOS transistors with a similar gate stack, the notched gate pMOSFETs exhibited an expected reduction of the parasitic overlap capacitances.As the rapid down-scaling of gate length of metal-oxidesemiconductor field-effect-transistors ͑MOSFETs͒ continues, 1 the nonscalable extrinsic parasitic capacitance and resistance components become comparable to the scaled intrinsic ones. These parasitic components constitute a main obstacle to achieving the desired high frequency performance of the transistors. The parasitic capacitance is composed mainly of two overlap capacitances at the two gate edges from the gate to the source/drain extension beneath the gate oxide, and the gate to source/drain fringing capacitances, as shown schematically in Fig. 1a. The overlap capacitances, determined by the gate oxide thickness and overlap distance, are becoming the predominant part of the overall parasitic capacitance as the effective oxide thickness ͑EOT͒ continues to decrease. Notched-gate technology has been proposed recently to reduce the overlap capacitances and therefore the parasitic capacitance especially at the drain side ͑as shown in Fig. 1b͒, so as to control the Miller capacitance ͑gate-to-drain capacitance͒ and enhance the high frequency performance of the transistors. 2-5 Methods of formation of a notched gate by selective plasma ͑dry͒ or wet underetch of bilayered gate electrodes on SiO 2 have been demonstrated. 3,4 In the meantime, metal gate and dielectrics of high relative dielectric constant ͑high-͒ are expected to replace the traditional poly-Si and SiO 2 gate stack to reduce the EOT while maintaining acceptable low gate leakage current through the gate dielectrics. 1,6 In this article, we demonstrate the formation of notched-gate pMOSFET with an atomic layer deposition ͑ALD͒ TiN metal gate and an ALD Al 2 O 3 /HfO 2 /Al 2 O 3 high-nanolaminate gate dielectric. After adding a p ϩ poly-SiGe layer on top of the ALD TiN, the notched gate was realized by using plasma dry etch of the polySiGe/TiN bilayer gate electrode, followed by a selective wet etch of the ALD TiN layer making an undercut beneath the SiGe. The fabricated notched-gate pMOSFETs were characterized both physically and electrically. ExperimentalThe devices were fabricated on 100 mm p-type Si substrates using a conventional complementary metal-oxide-semiconductor ͑CMOS͒ process. After n-type well formation, a high-nanolaminate structure of Al 2 O 3 /HfO 2 /Al 2 O 3 ͑with target thicknesses of 0.5/ 4/0.5 nm͒ was deposited on ...

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confidence: 99%

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confidence: 99%

Notched-Gate pMOSFET with ALD TiN/High-κ Gate Stack Formed by Selective Wet Etching

Hellström

Östling

et al. 2004

Electrochem. Solid-State Lett.

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Mobility Modulation Technology Impact on Device Performance and Reliability for <100> sub-90nm SOI CMOSFETs

Lai¹,

Lin²,

Yeh³

et al. 2005

Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials

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Introduction<100> channel orientation substrate and high tensile stress gate capping layer (GC liner-SiN) have been adapted for the mobility improvement of CMOSFETs [1][2][3][4]. There are few reports studying the effects of GC liner-SiN film thickness on device's characteristic and reliability. In this work, the impacts of high tensile stress GC liner-SiN thicknesses on device performance and hot-carrier induced degradations for 90nm PD-SOI CMOSFETs were investigated. We also inspect the stress come from GC liner-SiN and STI edge impact on device characteristic using the length of diffusion (LOD) check. ExperimentsPD-SOI CMOSFETs were fabricated on <100> channel orientation SOI substrate based on advanced 90nm CMOSFETs process with 200nm buried oxide layer (BOX) and 40nm Si layer using STI isolation technology. Sub-90nm devices were fabricated with different thicknesses of high tensile stress GC liner-SiN layer (700A, 1100A) and LOD (0.45µm~4.5µm). Device measurements and hot-carrier stressing were performed on probe station using various drain voltages (V D =0~1.4V), and various gate voltages (V G =0~1.4V) with 100 minutes hot-carrier stress time. Figure 1 shows the control methods of stress orientation. High stress liner-SiN induces a tensile stress in channel region, and STI induces a compressive one. From previous studies [1], it is found that <100> channel orientation substrate will enhance the mobility of pMOSFET and channel tensile stress induced by GC liner-SiN layer will enhance the mobility of nMOSFET; besides, a thicker (140A) liner-SiN layer will induce higher stress and improve the device performance [2]. However, in this work we found that thick GC liner-SiN layer (1100A) have no apparent improvement on device performance. The threshold voltage (V TH ) roll-off of 90nm BC-SOI nMOSFETs was shown in Fig. 2. It is obvious that devices with 700A GC liner-SiN layer have a lower V TH and a smaller V TH roll-off than devices with 1100A GC liner-SiN layer. And devices with 700A GC liner-SiN also possess smaller subthreshold swing and better I on -I Off characteristics than 1100A ones ( Fig.3 and 4). The I D -V D characteristics of 90nm BC and FB-SOI nMOSFETs are shown in Fig. 5. For body-tied device (BC-SOI), it is apparent that devices with GC liner-SiN possess larger drain current density (I D ) than conventional devices (SiN 380) does, and I D in 700A device is much larger than that in 1100A one. Compared with BC-SOI, I D of FB-SOI is high because of the floating body effect, and 700A devices possess the highest I D . There are no apparent different between conventional (SiN 380) and 1100A GC liner-SiN devices. Same tendency was found in G m characteristic (Fig. 6). In this work, larger mobility can be found on device with 700A GC liner-SiN. Figure 7 shows the I D -V D characteristics of 90nm BC-SOI nMOSFETs after 100min hot-carrier stressing. Because device's V TH shifted after hot-carrier stressing, as shown in Fig. 8; thus, I D rises apparently after hot-carrier stressing first and then degrades fina...

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Effects of gate notching profile defect on performance characteristics of short-channel NMOSFET with channel length of 0.12 μm

Seo

Yang

Kim

et al. 2003

IEEE Electron Device Lett.

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A notched metal gate MOSFET for sub-0.1 μm operation

Cited by 3 publications

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Notched-Gate pMOSFET with ALD TiN/High-κ Gate Stack Formed by Selective Wet Etching

Notched-Gate pMOSFET with ALD TiN/High-κ Gate Stack Formed by Selective Wet Etching

Mobility Modulation Technology Impact on Device Performance and Reliability for <100> sub-90nm SOI CMOSFETs

Effects of gate notching profile defect on performance characteristics of short-channel NMOSFET with channel length of 0.12 μm

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