A novel 10T SRAM cell for low power circuits

Abstract

This paper presents on the analysis of static and d y namic power dissipations in the proposed lOT SRAM cell. In the proposed structure two voltage sources, one connected with the Bit line and the other connected with the Bit bar line for reducing the voltage swing during the switching activit y . This reduction in voltage swing causes less d y namic power dissipation during switching activit y . Two stack transistors are also connected in the pull-down paths which result in increase in the threshold voltage of the transistors and thus cause the reduction in static power dissipation. Simulation has been done in 90nm CMOS technolog y with 1 volt p ower su pp l y in Microwind 3.1 software. Simulation results have been compared with those of other existing SRAM cells.