A Novel 1D-Convolution Accelerator for Low-Power Real-time CNN processing on the Edge

Sanchez, Justin; Soltani, Nasim; Chamarthi, Ramachandra Vikas; Sawant, Adarsh; Tabkhi, Hamed

doi:10.1109/hpec.2018.8547530

Cited by 6 publications

(4 citation statements)

References 40 publications

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“…Sanchez et al [ 62 ] introduce a novel algorithm architecture approach to enable real-time low-power CNN processing on edge devices. The core of the proposed approach is utilizing 1D dimensional convolution with an architecture that can truly benefit from the algorithm optimization.…”

Section: Answering the Rqsmentioning

confidence: 99%

A Systematic Literature Review on Distributed Machine Learning in Edge Computing

Filho

Marques

Chang

et al. 2022

Sensors

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Distributed edge intelligence is a disruptive research area that enables the execution of machine learning and deep learning (ML/DL) algorithms close to where data are generated. Since edge devices are more limited and heterogeneous than typical cloud devices, many hindrances have to be overcome to fully extract the potential benefits of such an approach (such as data-in-motion analytics). In this paper, we investigate the challenges of running ML/DL on edge devices in a distributed way, paying special attention to how techniques are adapted or designed to execute on these restricted devices. The techniques under discussion pervade the processes of caching, training, inference, and offloading on edge devices. We also explore the benefits and drawbacks of these strategies.

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Section: Answering the Rqsmentioning

confidence: 99%

A Systematic Literature Review on Distributed Machine Learning in Edge Computing

Filho

Marques

Chang

et al. 2022

Sensors

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show abstract

“…These problems mostly crop up in the first few layers where the number of pixels in the input tensor is large resulting in the massive computation and vector-to-matrix transformation. Sanchez et al demonstrates efficient hardware architecture to optimize original 2D convolution by incorporating the 1D architecture, primarily in the first few layers [32]. In this design, authors argued to keep the kernel data in the on-chip SRAM and the reduction of this total amount is made to be possible by using 1D convolution kernels for the first few layers.…”

Section: State-of-the-art Hardware Architectures For Convolutional Ne...mentioning

confidence: 99%

“…Sanchez et al [32] Presents an optimization technique to convert 2-D convolution into 1-D convert to avoid the transformation of vectors into matrices by using different vectors for the rows of the matrix and then added to minimize energy consumption, computation and latency.…”

Section: State-of-the-art Hardware Architectures For Convolutional Ne...mentioning

confidence: 99%

From DNNs to GANs: Review of efficient hardware architectures for deep learning

Bhattacharya¹

2021

Preprint

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In recent times, the trend in very large scale integration (VLSI) industry is multi-dimensional, e.g. reduction of energy consumption, occupancy of less space, precise result, less power dissipation, faster response etc. To meet these needs, the hardware architecture should be reliable and robust to these problems. Recently, neural network and deep learning has been started to impact the present research paradigm significantly which consists of parameters in the order of millions, nonlinear function for activation, convolutional operation for feature extraction, softmax regression for classification, generative adversarial networks, etc. These operations involve huge calculation and memory overhead. Presently available DSP processors are incapable of performing these operations and they most face the problems e.g. memory overhead, performance drop and compromised accuracy. Moreover, if a huge silicon area is powered to accelerate the operation using parallel computation, the IC's will be having significant chance of burning out due to the considerable generation of heat. Hence, novel dark silicon constraint is developed to reduce the heat dissipation without sacrificing the accuracy. Similarly, different algorithms have been adapted to design a DSP processor compatible for fast performance in neural network, activation function, convolutional neural network and generative adversarial network. In this review, we illustrate the recent developments in hardware for accelerating the efficient implementation of deep learning networks with enhanced performance. The techniques investigated in this review are expected to direct future research challenges of hardware optimization for high-performance computations.

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“…The last three decades have seen great success in understanding the ventral and dorsal pathways for the human visual cortex. These advances have motivated computer vision scientists to develop so-called "neuromorphic vision algorithms" for perception and cognition [1][2][3][4]. Neuromorphic models have shown high computing power and impressive performances with simple neural structures via reverse-engineering of the human brain.…”

Section: Introductionmentioning

confidence: 99%

A Systolic Accelerator for Neuromorphic Visual Recognition

Shuo

Wang

et al. 2020

Electronics

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Advances in neuroscience have encouraged researchers to focus on developing computational models that behave like the human brain. HMAX is one of the potential biologically inspired models that mimic the primate visual cortex’s functions and structures. HMAX has shown its effectiveness and versatility in multi-class object recognition with a simple computationalstructure. It is still a challenge to implement the HMAX model in embedded systems due to the heaviest computational S2 phase of HMAX. Previous implementations such as CoRe16 have used a reconfigurable two-dimensional processing element (PE) array to speed up the S2 layer for HMAX. However, the adder tree mechanism in CoRe16 used to produce output pixels by accumulating partial sums in different PEs increases the runtime for HMAX. To speed up the execution process of the S2 layer in HMAX, in this paper, we propose SAFA (systolic accelerator for HMAX), a systolic-array based architecture to compute and accelerate the S2 stage of HMAX. Using the output stationary (OS) dataflow, each PE in SAFA not only calculates the output pixel independently without additional accumulation of partial sums in multiple PEs, but also reduces the multiplexers applied inreconfigurable accelerators. Besides, data forwarding for the same input or weight data in OS reduces the memory bandwidth requirements. The simulation results show that the runtime of the heaviest computational S2 stage in HMAX model is decreased by 5.7%, and the bandwidth required formemory is reduced by 3.53× on average by different kernel sizes (except for kernel = 12) compared with CoRe16. SAFA also obtains lower power and area costs than other reconfigurable accelerators from synthesis on ASIC.

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A Novel 1D-Convolution Accelerator for Low-Power Real-time CNN processing on the Edge

Cited by 6 publications

References 40 publications

A Systematic Literature Review on Distributed Machine Learning in Edge Computing

A Systematic Literature Review on Distributed Machine Learning in Edge Computing

From DNNs to GANs: Review of efficient hardware architectures for deep learning

A Systolic Accelerator for Neuromorphic Visual Recognition

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