IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. 2005
DOI: 10.1109/csics.2005.1531749
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A novel 50-Gbit/s NRZ-RZ converter with retiming function using InP HEMT technology

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Cited by 7 publications
(2 citation statements)
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“…4. The NRZ-to-RZ converter has a master-slave topology formed by D-latch and AND circuits [10]. The latching operation ensures a wide phase margin between the NRZ data and the clock.…”
Section: Circuit Designmentioning
confidence: 99%
“…4. The NRZ-to-RZ converter has a master-slave topology formed by D-latch and AND circuits [10]. The latching operation ensures a wide phase margin between the NRZ data and the clock.…”
Section: Circuit Designmentioning
confidence: 99%
“…The NRZ-to-RZ converter is based on a master-slave topology formed of D-latch and AND circuits. 21) Since the circuit architecture is simple and the timing issue between input data and clock signals is not so serious, this type of PG is suitable for pursuing record performance with an immature cutting-edge device technology.…”
Section: Pg Architecture (Type I)mentioning
confidence: 99%