A novel 6H-SiC power DMOSFET with implanted p-well spacer

Vathulya, V.R.; Shang, Huiling; White, M.H.

doi:10.1109/55.772374

Cited by 14 publications

(4 citation statements)

References 11 publications

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“…The wide bandgap semiconductor properties of silicon carbide (SiC) make it a promising candidate for the development of future power switching devices [1,2]. This is primarily due to SiC possessing properties such as a strong breakdown field, high physical and chemical stability, high thermal conductivity, and high electron saturation velocity [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

A Novel Asymmetric Trench SiC Metal–Oxide–Semiconductor Field-Effect Transistor with a Poly-Si/SiC Heterojunction Diode for Optimizing Reverse Conduction Performance

Yu,

Cheng,

et al. 2024

Micromachines

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In this paper, a novel asymmetric trench SiC MOSFET with a Poly-Si/SiC heterojunction diode (HJD-ATMOS) is designed to improve its reverse conduction characteristics and switching performance. This structure features an integrated heterojunction diode, which improves body diode characteristics without affecting device static characteristics. The heterojunction diode acts as a freewheeling diode during reverse conduction, reducing the cut-in voltage (Vcut-in) to a lower level than conventional asymmetric trench SiC MOSFET (C-ATMOS), while maintaining a similar breakdown voltage. Meanwhile, the split gate structure reduces gate-to-drain charge (Qgd). Through TCAD simulation, the HJD-ATMOS decreases Vcut-in by 53.04% compared to the C-ATMOS. Both Qgd and switching loss are reduced, with a decrease of 31.91% in Qgd and 40.29% in switching loss.

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Section: Introductionmentioning

confidence: 99%

A Novel Asymmetric Trench SiC Metal–Oxide–Semiconductor Field-Effect Transistor with a Poly-Si/SiC Heterojunction Diode for Optimizing Reverse Conduction Performance

Yu,

Cheng,

et al. 2024

Micromachines

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“…JFET region design, including the JFET width and doping concentration, plays a crucial role in optimizing the

and switching performance of SiC MOSFETs [ 4 ]. Studies of JFET region design for 1

and

SiC MOSFETs [ 5 , 6 ] have demonstrated that optimizing JFET width and enhancing the doping concentration of the JFET region can reduce the JFET region resistance and lead to smaller

of SiC power MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs

et al. 2022

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650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal P+ layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance (Ron,sp) and lowers the gate-drain capacitance (Cgd). It was experimentally shown that a thinner gate oxide further reduces Ron,sp, although with a penalty in terms of increased Cgd. A design with 0.5 μm half JFET width, enhanced JFET doping concentration of 5.5×1016 cm−3, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices.

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“…On the (0001) Si face, the interface trap density (Dit) near the conduction band edge is high and the Dit strongly affects channel mobility [5]. Thus, the other approach to improving channel mobility is to use a specific surface for the channel region such as the (11 2 0) or (03 3 8) [6].…”

Section: Introductionmentioning

confidence: 99%

Low On-Resistance in Normally-Off 4H-SiC Accumulation MOSFET

Okuno

Endo

Matsuki³

et al. 2005

MSF

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In our previous paper [1], we simulated an accumulation-mode MOSFET with an epitaxial layer channel (epi-channel) that had a high channel mobility. In this paper, we experimentally show that channel mobility is enhanced by the epi-channel. On varying the thickness of the epi-channel, the channel mobility improved from a few cm2/Vs to 100 cm2/Vs. Finally, we show that the “Normally-off” accumulation MOSFET with a 720 V breakdown voltage has a low on-resistance (10.4 m1cm2) and that the 3 × 3 mm2 accumulation MOSFET operates over 10 A and its on-resistance is 19 m1cm2.

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A novel 6H-SiC power DMOSFET with implanted p-well spacer

Cited by 14 publications

References 11 publications

A Novel Asymmetric Trench SiC Metal–Oxide–Semiconductor Field-Effect Transistor with a Poly-Si/SiC Heterojunction Diode for Optimizing Reverse Conduction Performance

A Novel Asymmetric Trench SiC Metal–Oxide–Semiconductor Field-Effect Transistor with a Poly-Si/SiC Heterojunction Diode for Optimizing Reverse Conduction Performance

Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs

Low On-Resistance in Normally-Off 4H-SiC Accumulation MOSFET

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