For multilevel interconnects of LSI memory devices, the Al sprint process using the two-step cold/hot Al PVD at less than 400 • C is a realistic solution to reduction of the process cost. The process windows of via filling were investigated for via holes of 0.22 µm to 0.16 µm. Based on the assumption that Al diffusion decides filling capability, temperature and thickness of the cold Al liner PVD and deposition time of the hot Al PVD were optimized, resulting in complete filling of 0.16 µm via holes. We have confirmed the viability of the Al PVD via filling for less than 110 nm device generations.