A novel approach for constructing reversible fault tolerant n-bit binary comparator

A Universal Reversible Gate Architecture for Designing N-Bit Comparator Structure in Quantum-dot Cellular Automata

“…This reduced delay is possible because of both the proposed gates in the comparator function independently and the output R is not used in the comparator structure. 17 18 19 20 21 22 23 24 25 26 FT a7 a6 a7 a7 a4 a6 a4 a4 a6 a6 42% a2 a2 a3 a3 a0 a2 a0 a0 a2 a2 42% a5 a5 a5 a5 a6 a4 a4 a4 a4 a6 46% a5 a5 a5 a5 a7 a5 a5 a5 a5 a7 61% a1 a1 a1 a1 a1 a1 a1 a1 a3 a3 57% a0 a0 a0 a1 a0 a0 a0 a0 a2 a2 50% a7 a7 a7 a7 a7 a7 a7 a5 a5 a7 54% a3 a3 a3 a3 a3 a3 a3 a1 a1 a3 57% Table 7 compares the existing one-bit reversible QCA comparator [6] with the proposed one-bit comparator. The proposed comparator structure can be extended to any number of bits (i.e., n).…”

“…It would be important if the primitive's results used for layout design would be optimal. Existing comparator based on conventional logic based can still provide the design engineer with enough freedom to synthesize reversible logic design to best meet the energy free requirements of a specific application [6]. The reasons are, once there is designed by reversible gates in a circuit there must be quantum gates to compute the quantum information [7].…”

Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits

“…A fault tolerant design based on two new gates, the AG gate and the FTSEG gate was presented in an approach for constructing reversible n-bit comparator [8]. The design has three major parts; the first part being a MSB comparator circuit which compares the MSBs of two binary numbers.…”

“…This paper presents the design of n-bit reversible fault tolerant comparator. There are a few reversible comparators [6,7,8,9,10,11] but with number of garbage outputs being on the higher side. The proposed design outperforms the previous designs [8,10] in terms of garbage outputs and constant inputs.…”