A Novel Approach for Cooling Chiplets in Heterogeneously Integrated 2.5-D Packages Applying Microchannel Heatsink Embedded in the Interposer

Bognár, G.; Takács, Gábor; Szabó, Péter

doi:10.1109/tcpmt.2023.3298378

Cited by 2 publications

(2 citation statements)

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“…have delved into the optimization of a micro-TEC embedded within a cavity etched in the thermal interface material (TIM) layer atop a 3D integrated architecture and this setup connects to a heat spreader layer. Nevertheless, challenges emerge when photonic and electronic chips within a 2.5D configuration possess different thicknesses, leading to varying thicknesses of the TIM layer connected to the heat spreader 13 . This necessitates the redesign and fabrication of the micro-TEC with distinct thicknesses for effective thermal control of the photonic and electronic chips.…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, challenges emerge when photonic and electronic chips within a 2.5D configuration possess different thicknesses, leading to varying thicknesses of the TIM layer connected to the heat spreader. 13 This necessitates the redesign and fabrication of the micro-TEC Fig. 1 Schematic showing different approaches of thermoelectric cooler integration in a photonic package where photonic integrated chip (PIC) and electronic integrated chip (EIC) are copackaged together on a glass substrate where the implementation of (a) macro-thermoelectric cooler (Macro-TEC); (b) micro-TEC (μ-TEC); and (c) SimTEC in photonic packages is highlighted.…”

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confidence: 99%

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Substrate integrated micro-thermoelectric coolers in glass substrate for next-generation photonic packages

Gupta,

Tanwar,

et al. 2024

J. Optical Microsystems

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Managing the temperature of photonic chips within intricate electro-optic packages poses a notable challenge concerning the thermal crosstalk between the photonic chip, electronic chip, and the chip-fiber connection point. This is a multifaceted problem and requires packaging solutions that cannot only address high-performance thermal management but must also be scalable to high volumes. Glass has long been thought of as a suitable platform for next-generation photonic packaging due to its low thermal conductivity, which minimizes unwanted heat transfer between electronic and photonic components. Achieving proper thermal isolation between the chips and the chip-fiber interface necessitates a microscale thermal solution that guarantees accurate temperature regulation of the photonic circuitry without disrupting the optical coupling interface with the fiber array, due to the presence of epoxy used for fiber attachment. We propose a technique for the development of a substrate-integrated microthermoelectric cooler (SimTEC) for the effective temperature control of the electronic and photonic integrated devices. The proposed device uses glass substrate vias that are half-filled with p and n-type thermoelectric materials and the other half with copper. A COMSOL multiphysics model is developed to study the variations in the cooling performance of this SimTEC device based on changes in the via parameters. Interestingly, the maximum range of temperature gradient variation for SimTEC is 6 times greater compared to that of equivalent free-standing micro-TEC pillars. However, there are some challenges associated with implementing this method, as the temperature gradient (or cooling effect) achieved by SimTEC still falls short of that achieved by the free-standing micro-TEC pillars.

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Section: Introductionmentioning

confidence: 99%

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confidence: 99%