A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML

Abstract

System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the ambiguity of design specifications specified by different protocol standards in general and JEDEC memory protocol standards in specific imposes numerous difficulties on designers and verification engineers when translating design specifications into SVA. This motivated us to find a simple way to capture design specifications from JEDEC standard and automatically generate SVA that can be used as checkers for DDR memory protocols. In this paper, we propose a new method to capture design specifications using a timing diagram tool that documents the captured design specifications in a Timing Diagram Markup Language (TDML) based format and generate SVA from the TDML document. The viability and the potential of our work are demonstrated with an Industrial case study using JEDEC LPDDR3 Memory Protocol Standard.

An expert system for checking the correctness of memory systems using simulation and metamorphic testing

“…Kayed et al presented a novel approach based on the JEDEC standards . This way, to verify the validity of the generated commands, the timing constraints are defined using a Timing Diagram Mark up Language and transformed into system Verilog assertions Kayed et al (2014). Li et al proposed the modelling and verification of dynamic command scheduling for real-time memory controllers Li et al (2016).…”

“…Although there are numerous advantages related to the use of model checking for analysing the correctness of systems, like the high coverage it achieves, the previously described ap-proaches entail different issues, which are alleviated by our proposed system. First, these solutions are focused on verifying memory controllers with an ad-hoc model design and, therefore, these require specific requirements for each design, like a reference TLM model Khalifa & Salah (2015) and a specific register-transfer level implementation Kayed et al (2014). Hence, in order to successfully achieve a new version of the scheduler, several temporal logic constraints must be re-adapted and re-written for each memory controller.…”

Complete Properties Extraction from Simulation Traces for Assertions Auto-generation

“…Recently, many research efforts are introduced either for assertions auto-generation [9] - [15] or for assertions auto-debugging [16]. Automatic generation of meaningful true assertions can save at least about 40% of design verification time cycle.…”

“…It is based on a state- Due to the ambiguity of design specifications specified by different protocol standards, new approaches for assertions generation are dedicated for specific protocol standards. The approach presented by [15] is dedicated for SVA generation of DDR memory protocols. The proposed method captures design specifications using a timing diagram tool that can extract the sequence of timing events necessary to build SVA for DDR protocol.…”