A Novel Approach for Test Pattern Generation using ALU

Kaarthik, K; Vivek, C; Sivaranjani,

doi:10.1109/icaccs57279.2023.10112947

2023 9th International Conference on Advanced Computing and Communication Systems (ICACCS) 2023

DOI: 10.1109/icaccs57279.2023.10112947

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A Novel Approach for Test Pattern Generation using ALU

K Kaarthik¹,

C Vivek

Sivaranjani Sivaranjani³

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Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Mohanarangam,

M Shirur

et al. 2023

Electronics

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Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW.

show abstract

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Mohanarangam,

M Shirur

et al. 2023

Electronics

View full text Add to dashboard Cite

show abstract

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A Novel Approach for Test Pattern Generation using ALU

Cited by 1 publication

References 10 publications

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

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