A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures

Liu, Leibo; Ren, Yuchen; Deng, Chenchen; Yin, Shouyi; Wei, Shaojun; Han, Jie

doi:10.1109/aspdac.2015.7058980

Cited by 8 publications

(2 citation statements)

References 17 publications

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“…First, redundant resources could replace the faulty ones by transforming the mapping result equivalently. Thus, CGRAs can provide fault-tolerant designs against a low-yield process and physical failures [162][163][164][165], making it suitable for applications that have a high requirement for fault tolerance, such as aerospace and high-end servers. Second, the redundant resources can implement security check modules to avoid physical attacks and hardware trojans [166].…”

Section: Prospective Evolutions Of Applicationsmentioning

confidence: 99%

A Survey of Coarse-Grained Reconfigurable Architecture and Design

et al. 2019

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As general-purpose processors have hit the power wall and chip fabrication cost escalates alarmingly, coarsegrained reconfigurable architectures (CGRAs) are attracting increasing interest from both academia and industry, because they offer the performance and energy efficiency of hardware with the flexibility of software. However, CGRAs are not yet mature in terms of programmability, productivity, and adaptability. This article reviews the architecture and design of CGRAs thoroughly for the purpose of exploiting their full potential. First, a novel multidimensional taxonomy is proposed. Second, major challenges and the corresponding state-of-the-art techniques are surveyed and analyzed. Finally, the future development is discussed. CCS Concepts: • Computer systems organization → Reconfigurable computing; • Hardware → Reconfigurable logic and FPGAs; • Theory of computation → Models of computation;

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Section: Prospective Evolutions Of Applicationsmentioning

confidence: 99%

A Survey of Coarse-Grained Reconfigurable Architecture and Design

et al. 2019

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“…On the routing-based table algorithm, the path that a message will go through is determined by querying the routing tables [6]. This implementation is often used for irregular networks routing.…”

Section: Basics Of Sbr and Rbrmentioning

confidence: 99%

Efficient routing table minimization for fault-tolerant irregular Network-on-Chip

Mota

Silveira

Brahm

et al. 2016

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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Table-based routing is a common approach for a fault-tolerant Network-on-Chip (NoC). This approach is hard to scale, since the table size tends to grow according to the NoC size. To surpass this problem, some works, such as the Region-Based Routing (RBR), have proposed techniques for saving routing tables area. This work proposes an alternative routing technique finding among communication pairs selected by the RBR technique, shrinking the amount of bits used for setting up regions. The experimental results have shown that the proposed technique reduces the maximum and mean number of regions, decreasing the space used by routing tables, providing more scalable and efficient routing NoC.

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