A novel architecture for low voltage-low power DLL-based frequency multipliers

Gholami, Mohammad; Ardeshir, Gholamreza; Ghonoodi, Hojat

doi:10.1587/elex.8.859

Cited by 14 publications

(7 citation statements)

References 6 publications

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“…Here, the comparator is a block which its role is to convert the error signal to a readable data for DSP. There are a decoder (3)(4)(5)(6)(7)(8) and some switches which are used to select the feedback path for each channel. For example, to select second channel with f REF = 16 MHz, N = 23, M = 2, selectors of decoder should be as S 2 S 1 S 0 = 010.…”

Section: Proposed Novel All-digital Dll-based Frequency Synthesiser Fmentioning

confidence: 99%

Digital delay locked loop‐based frequency synthesiser for Digital Video Broadcasting‐Terrestrial receivers

Gholami¹,

Rahimpour²,

Ardeshir³

et al. 2014

IET Circuits, Devices & Systems

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In this study, the authors cover French very high frequency (VHF) band with a novel all-digital fast lock delayed looked loop (DLL)-based frequency synthesiser. Since this new architecture uses a digital signal processing unit instead of phasefrequency detector, charge pump and loop filter in conventional DLL therefore it shows better jitter performance, locktime and convergence speed. To obtain in-phase input and output signals in DLLs, optimisation methods are used in the proposed architecture. The proposed architecture is designed to cover channels of French VHF band by choosing number of delay cells in signal path. Simulation has been done for 22-27 delay cells and f REF = 16 MHz which can produce output frequency in range of 176-216 MHz. Locking time is approximately 0.5 μs which is equal to 8 clock cycles of reference clock. All of simulation results show superiority of the proposed structure.

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Section: Proposed Novel All-digital Dll-based Frequency Synthesiser Fmentioning

confidence: 99%

Digital delay locked loop‐based frequency synthesiser for Digital Video Broadcasting‐Terrestrial receivers

Gholami¹,

Rahimpour²,

Ardeshir³

et al. 2014

IET Circuits, Devices & Systems

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“…It consists of comparator, buffer, substractor, DSP, delay cells, exclusive OR gates, two three-input ORs, frequency divider, a decoder, and some switches. There are decoders (3)(4)(5)(6)(7)(8) and some switches that are used to select the feedback path for each channel. For example, to select second channel with f REF = 16 MHz, N = 23, and M = 2, selectors of decoder should be S 2 S 1 S 0 = 010.…”

Section: Proposed Fast-lock Low-jitter and All-digital Frequency Symentioning

confidence: 99%

“…Delay‐locked loops (DLLs) and phased‐locked loops (PLLs) are widely used in clock synchronization circuits , frequency synthesizers , digital transceivers , Dynamic Random‐Access Memory (DRAMs) , Static Random‐Access Memory (SRAMs) , and clock and data recovery circuits . DLLs offer better jitter performance than PLLs .…”

Section: Introductionmentioning

confidence: 99%

A new fast‐lock, low‐jitter, and all‐digital frequency synthesizer for DVB‐T receivers

Gholami

Rahimpour

Ardeshir

et al. 2013

Circuit Theory & Apps

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SUMMARYLock time and convergence time are the most important challenges in delay-locked loops (DLLs). In this paper we cover French very high frequency band with a novel all-digital fast-lock DLL-based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22-27 delay cells, and f REF = 16 MHz, which can produce output frequency in range of 176-216 MHz. Locking time is approximately 0.3 μs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure.

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“…Nowadays, Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are widely used in high-speed systems, frequency synthesizers [1,2], RAM [3], clock synchronization and clock and data recovery circuits [4]. They are unavoidable parts in communication systems.…”

Section: Introductionmentioning

confidence: 99%

Dual Phase Detector Based Delay Locked Loop for High Speed Applications

Gholami

Ardeshir

2014

IJE

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In this paper a new architecture for delay locked loops is proposed. Static phase offset and reset path delay are the most important problems in phase-frequency detectors (PFD). The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and output of the DLL. Near locking, an XOR gate is used to act as a PFD which makes the DLL locks with less jitter. Also, the reset path time and glitch are decreased by using the XOR gate. The proposed architecture has been designed in TSMC 0.18um CMOS Technology. The simulation results support the theoretical design aspects.

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A novel architecture for low voltage-low power DLL-based frequency multipliers

Cited by 14 publications

References 6 publications

Digital delay locked loop‐based frequency synthesiser for Digital Video Broadcasting‐Terrestrial receivers

Digital delay locked loop‐based frequency synthesiser for Digital Video Broadcasting‐Terrestrial receivers

A new fast‐lock, low‐jitter, and all‐digital frequency synthesizer for DVB‐T receivers

Dual Phase Detector Based Delay Locked Loop for High Speed Applications

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