A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture

Han, Xueyu; Chen, Jiajia; Qin, Boyu; Rahardja, Susanto

doi:10.1109/tcad.2020.2978839

Cited by 16 publications

(2 citation statements)

References 36 publications

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“…Much work has been focused on reducing memory demands. Computing twiddle factors on-chip has been explored [33,35,62] and applied in industry [90]. In-memory FFT accelerators have also been proposed to reduce this communication overhead [36,81,138] along with 3D-stacked memory accelerators [60].…”

Section: Fft Acceleratorsmentioning

confidence: 99%

Bind the gap: compiling real software to hardware FFT accelerators

Woodruff

Armengol-Estapé

Ainsworth

et al. 2022

Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation

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Specialized hardware accelerators continue to be a source of performance improvement. However, such specialization comes at a programming price. The fundamental issue is that of a mismatch between the diversity of user code and the functionality of fixed hardware, limiting its wider uptake.Here we focus on a particular set of accelerators: those for Fast Fourier Transforms. We present FACC (Fourier ACcelerator Compiler), a novel approach to automatically map legacy code to Fourier Transform accelerators. It automatically generates drop-in replacement adapters using Input-Output (IO)-based program synthesis that bridge the gap between user code and accelerators. We apply FACC to unmodified GitHub C programs of varying complexity and compare against two existing approaches. We target FACC to a high-performance library, FFTW, and two hardware accelerators, the NXP PowerQuad and the Analog Devices FFTA, and demonstrate mean speedups of 9x, 17x and 27x respectively.

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Section: Fft Acceleratorsmentioning

confidence: 99%

Bind the gap: compiling real software to hardware FFT accelerators

Woodruff

Armengol-Estapé

Ainsworth

et al. 2022

Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation

View full text Add to dashboard Cite

show abstract

“…Approximate multipliers have also been employed by [12] to improve the accuracy and hardware efficiency of neural networks. The impact of approximate computing in the design of an efficient FFT architecture is discussed in [13]; and hybrid approximate adders have been studied in [14] for energy-efficient image and video processing accelerators, where up to 73% energy reduction has been reported. By matching the statistical error attributes of the hardware with the statistical processing requirements of the target application, a tremendous gain can be achieved.…”

Section: A Approximate Computing: Achieving Energy Efficiency From Th...mentioning

confidence: 99%

Combination of Task Allocation and Approximate Computing for Fog-Architecture-Based IoT

Najafi

Huang

et al. 2021

IEEE Internet Things J.

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Achieving energy efficiency is always a primary concern for fog-architecture-based Internet of Things (IoT) applications. As the IoT devices are typically of small sizes and powered by battery energy, it is essential to address the energy consumption at all levels from the circuit to the system. Two of the promising solutions at circuit and system levels are approximate computing and energy-aware task allocation, respectively. However, the existing task allocation approaches are designed without considering the aspect of approximate computing. In this work, we fill this gap and aim to maximize the network lifetime subject to the accuracy requirements of the applications. By considering both the approximate computing and task allocation simultaneously, a nonlinear problem is obtained to allocate the tasks for the devices (fog nodes and IoT end devices) and to select the corresponding execution modes (tasks in approximate or exact modes). To efficiently solve this problem, a centralized algorithm is first proposed by transferring the above nonlinear problem as a linear programming (LP) problem. As executing the centralized algorithm is a challenge for the resource-limited IoT devices, this work further proposes an optimal distributed algorithm based on Dantzig-Wolfe decomposition to solve the problem of tasks distribution and execution modes selection. The centralized large-scaled LP problem is decomposed into smallscaled subproblems, which can be efficiently solved by each IoT device. The proposed algorithms are tested by extensive simulations. The results demonstrate that the distributed algorithm achieves the same results as the centralized algorithm, and both of them significantly outperform the previous approaches.

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Design of High‐Performance Radix‐Power‐of‐2 Butterfly Architectures for FFT Implementation by Cosine Coefficients Extraction

Moni Varghese,

Sundaram

2024

Circuit Theory & Apps

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Designing FFTs with higher radix butterfly units are increasingly in demand to combat the high throughput of 20 Gbps of the current 5G and 1 Tbps for beyond 5G technologies. Previous higher radix FFTs were implemented in FPGA, giving importance to area and power. This paper presents the design of radix‐power‐of‐2 butterfly circuit, using the proposed radix cosine coefficients' extractor equation that is applicable to all the inputs. This enables efficient pipelined shift‐add implementation of the required complex rotations. The proposed methodology encompasses the implementation of any power‐of‐two‐radix butterfly to realize large size FFT, essential for real‐time 5G and 6G applications. The proposed radix‐4, radix‐8, radix‐16, and radix‐32 architectures are implemented and verified on Xilinx Spartan‐7 FPGA using Vivado Design Suite (v2018). The results demonstrate that the proposed radix‐16 and radix‐32 architectures achieve a higher clock frequency, by a factor of 5.23 and 6.76, respectively, compared to the most recent literature. For performance analysis, the area‐delay and power‐delay products of the proposed radix‐16 and radix‐32 butterfly architecture are computed. The proposed radix‐16 butterfly architecture exhibits a 13.3% reduction in area‐delay product and a 34.25% decrease in power‐delay product compared to recent literatures. Similarly, the radix‐32 architecture shows a 27.31% lower area‐delay product and a 0.63% lower power‐delay product.

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A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture

Cited by 16 publications

References 36 publications

Bind the gap: compiling real software to hardware FFT accelerators

Bind the gap: compiling real software to hardware FFT accelerators

Combination of Task Allocation and Approximate Computing for Fog-Architecture-Based IoT

Design of High‐Performance Radix‐Power‐of‐2 Butterfly Architectures for FFT Implementation by Cosine Coefficients Extraction

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