A novel ASIC design approach based on a new machine paradigm

Hartenstein, Reiner W.; Hirschbiel, A. G.; Riedmuller, M.; Schmidt, K.; Weber, Matthias

doi:10.1109/4.92017

Cited by 45 publications

(19 citation statements)

References 3 publications

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“…Thus the destinations of jumps are not instructions but data objects [58]. As well as the von Neumann paradigm guaranties universality of its processors, an existing d-paradigm garanties the universality of d-processors [59] - [62].…”

Section: Figure 9 Comparisons Of Different Computing Paradigmsmentioning

confidence: 99%

<title>Codesign and high-performance computing: scenes and crisis</title>

et al. 1996

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Section: Figure 9 Comparisons Of Different Computing Paradigmsmentioning

confidence: 99%

<title>Codesign and high-performance computing: scenes and crisis</title>

et al. 1996

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“…This makes use of a property of the DCT to produce small values (often quantized to zero) towards the lower right corner of the eight-by-eight block. Long sequences of zeros can be expected AC [7,7] a) Figure 12. Preparation of quantized coefficients: a) differential DC encoding; b) zig-zag scan…”

Section: Run Length Coding and Huffmann Codingmentioning

confidence: 99%

“…The key concept of an Xputer [2], [7] is to map the structure of performance critical algorithms into the hardware architecture. Performance critical algorithms typically apply the same set of operations to a large amount of data.…”

Section: Xputermentioning

confidence: 99%

<title>Reconfigurable machine for applications in image and video compression</title>

Hartenstein

Becker

Kress

et al. 1995

Advanced Image and Video Communications and Storage Technologies

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This paper presents a reconfigurable machine for applications in image or video compression. The machine can be used stand alone or as a universal accelerator co-processor for desktop computers for image processing. It is well suited for image compression algorithms such as JPEG for still pictures or for encoding MPEG movies. It provides a much cheaper and more flexible hardware platform than special image compression ASICs and it can substantially accelerate desktop computing.

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“…The rALU allows for each application a quick problem-oriented reconfiguration. High performance improvements have been achieved for the class of regular, scientific computations [5], [1]. An Xputer consists of three major parts: the data sequencer, the data memory and the rALU including multiple scan windows and operator subnets.…”

Section: Utilisation With the Xputer Hardware Environmentmentioning

confidence: 99%

A new FPGA architecture for word-oriented datapaths

Hartenstein

Kress

Reinig

1994

Field-Programmable Logic Architectures, Synthesis and Applications

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Abstract.A new FPGA architecture (reconfigurable datapath architecture, rDPA) for word-oriented datapaths is presented, which has been developed to support a variety of Xputer architectures. In contrast to von Neumann machines an Xputer architecture strongly supports the concept of the "soft ALU" (reconfigurable ALU). Fine grained parallelism is achieved by using simple reconfigurable processing elements which are called datapath units (DPUs). The wordoriented datapath simplifies the mapping of applications onto the architecture. Pipelining is supported by the architecture. It is extendable to almost arbitrarily large arrays and is in-system dynamically reconfigurable. The programming environment allows automatic mapping of the operators from high level descriptions. The corresponding scheduling techniques for I/O operations are explained. The rDPA can be used as a reconfigurable ALU for bus-oriented host based systems as well as for rapid prototyping of high speed datapaths.

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A novel ASIC design approach based on a new machine paradigm

Cited by 45 publications

References 3 publications

<title>Codesign and high-performance computing: scenes and crisis</title>

<title>Codesign and high-performance computing: scenes and crisis</title>

<title>Reconfigurable machine for applications in image and video compression</title>

A new FPGA architecture for word-oriented datapaths

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