2021 Ieee Urucon 2021
DOI: 10.1109/urucon53396.2021.9647360
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A Novel Asynchronous Pipeline Architecture with Less-Registers Using NULL Convention Logic

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“…One famous technique used by digital designers to raise the throughput of circuits is the pipeline, which divides the circuit into stages with the insertion of registers to hold partial values. Asynchronous pipelines have four considerable advantages over synchronous pipelines [5]: (1) In a synchronous pipeline the clock frequency is calculated using the critical path of the circuit and all stages operates in the same rate, while in the asynchronous one, each stage operates accordingly with its own critical path, reducing the latency time.…”
mentioning
confidence: 99%
“…One famous technique used by digital designers to raise the throughput of circuits is the pipeline, which divides the circuit into stages with the insertion of registers to hold partial values. Asynchronous pipelines have four considerable advantages over synchronous pipelines [5]: (1) In a synchronous pipeline the clock frequency is calculated using the critical path of the circuit and all stages operates in the same rate, while in the asynchronous one, each stage operates accordingly with its own critical path, reducing the latency time.…”
mentioning
confidence: 99%