A novel bottom–up copper filling of blind silicon vias in 3D electronic packaging

Abstract

Through silicon via is a promising technology that has benefits of high density, excellent performance and heterogeneous integration for 3D stacked devices, where blind silicon via plating in via first and via middle approaches is widely used. However, using conventional damascene copper plating technology to achieve high quality copper filling of blind vias is very difficult. In this paper, we demonstrate a novel approach for realizing bottom–up copper filling of blind silicon vias. Electroplating of the blind vias is carried out by using a titanium barrier layer, instead of the traditional copper seed layer, as the conductive medium. A vacuum process is introduced to push photoresist completely into the blind vias. By controlling the exposure and development processes, the photoresist at the top and middle of the vias is removed while that at the bottom it is retained for protecting the seed layer. After etching the exposed seed layer, we obtain a unique metal layer structure in which the copper seed layer is reserved at the via bottom, facilitating spontaneous bottom–up plating. Using this approach, we realize high quality copper filling of blind silicon vias of 30 µm in diameter and 120 µm in depth, which will be of noteworthy benefit in 3D electronic packaging.

Mathematical model of a novel small magnetorheological damper by using outer magnetic field

“…[10][11][12][13] For example, bonding pressure of microelectronics packaging equipment needs to be applied to the stable load of 5N, [14][15][16][17][18] and damping force of micro-mechanical damping system is only 20N. 19,20 Recently, some small MRF dampers are developed, such as the RD-1097-01X damper is the smallest commercial damper, whose force is still 100N.…”

Challenges facing copper‐plated metallisation for silicon photovoltaics: Insights from integrated circuit technology development

“…Whereas Cu electroplating of interconnects for earlier IC devices involved trench (blind via) conformal plating using damascene chemistry, bottom‐up plating approaches are being developed for the high aspect ratio TSVs required for 3D‐IC applications (see Figure ). Bottom‐up plating makes it easier to achieve void‐free interconnectors and allows higher aspect ratio structures to be formed .…”

Atomistic Investigation on the Blocking Phenomenon of Crack Propagation in Cu Substrate Reinforced by CNT

“…Recently, the semiconductor industry has been attempting to design semiconductors in three dimensions (3Ds); as a result, the importance of 3D electronic packaging has also been highlighted [ 1 ]. Stacking semiconductors in 3Ds through silicon via (TSV) technology (not previously used) is being used currently [ 2 ]. When TSV technology is used, copper (Cu) is generally filled in a space through which silicon can penetrate for electric conduction.…”