A novel cell structure suitable for a 3 volt operation, sector erase flash memory

Onoda,; Kunori,; Kobayashi, Kazuya; Ohi,; Fukumoto,; Ajika,; Miyoshi,

doi:10.1109/iedm.1992.307432

Cited by 26 publications

(2 citation statements)

References 4 publications

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“…DINOR cells [78] (Fig. 36) are common ground cells fabricated with a triple-well, triple-level polysilicon, a tungsten plug, and two layers of metal.…”

Section: Divided Bit-line Normentioning

confidence: 99%

Flash memory cells-an overview

et al. 1997

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“…DINOR cells [78] (Fig. 36) are common ground cells fabricated with a triple-well, triple-level polysilicon, a tungsten plug, and two layers of metal.…”

Section: Divided Bit-line Normentioning

confidence: 99%

Flash memory cells-an overview

et al. 1997

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“…5 d final silicon thickness and a 4 d buried oxide. The memory cell for both SO1 and bulk CMOS is a selfaligned one-transistor flash EEPROM based on an embedded 0.4p.m double-poly CMOS technology with Fowler-Nordheim (FN) tunneling is utilized for program and erase operations, similar to that of the DINOR cell [6]. For programming, the bitcell is written to the low state by tunneling electrons from the floating gate to the drain which underlaps the gate.…”

mentioning

confidence: 99%

An advanced flash memory technology on SOI

Burnett

Shum²,

Baker³

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

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For the first time, EEPROM functionality is demonstrated on double-poly bitcells on SO1 using the same layout as standard bulk CMOS bitcells. By using FN tunneling for program and erase (PE) operations, the P E characteristics of the floating-body SO1 bitcell are comparable to the bulk CMOS characteristics. Bitcell endurance for SO1 cells show significantly less window closure than bulk CMOS cells. High-voltage SO1 device characteristics are also compared with bulk devices. With sufficient body contacts, the high-voltage SO1 devices can support the required bitcell voltages.LOCOS-based isolation for bulk and a modified PBL isolation for SO1 [5]. The bitcell has a tunnel oxide of 95A and an equivalent ONO thickness of I8OA. Figures I(a) and l(b) show SEM cross-sections along the bitline and wordline of a SO1 bitcell array. As seen in the figures, the body of the bitcell is completely floating as it uses the same layout as a standard bulk CMOS bitcell. The high-voltage devices have a 240A gate oxide thickness and use a hard arsenic S/D with a phosphorus co-implant. SO1 high-voltage devices were fabricated with final silicon thicknesses of l d and 1.5kA for comparison with bulk CMOS devices. BITCELL CHARACTERISTICS INTRODUCTIONBecause of the improved performance and reduced power consumption achievable with SO1 technology, a significant effort has been focused on SO1 development resulting in functional DRAMS, SRAMs, microcontroller cores, and microprocessor cores on SO1 [l-41. However, for general embedded applications and future system-on-achip solutions, Flash EEPROM functionality must be offered. Despite the tremendous circuit achievements on RAM and logic circuits, no one has demonstrated even a functional NVM bitcell on SO1 using a conventional double-poly process. In this work, we report on the functionality of double-poly NVM bitcells fabricated on SOI. Because of the large voltages required to provide electrical programming and erasure, the peripheral highvoltage (HV) devices must support the required voltages. Due to the decreased breakdown voltages of SO1 HV NMOS transistors, special source-body tie devices are utilized to significantly improve the breakdown voltages. PROCESS DESCRIPTIONThe SO1 devices were fabricated on SIMOX substrates with 1 . 5 d final silicon thickness and a 4 d buried oxide. The memory cell for both SO1 and bulk CMOS is a selfaligned one-transistor flash EEPROM based on an embedded 0.4p.m double-poly CMOS technology with Fowler-Nordheim (FN) tunneling is utilized for program and erase operations, similar to that of the DINOR cell [6]. For programming, the bitcell is written to the low state by tunneling electrons from the floating gate to the drain which underlaps the gate. Single-device breakdown would be a likely problem with conventional hot-carrier programming. As shown in Figure 2, the program characteristics for the floating-body cell are identical to that of the bulk CMOS bitcell. For erasure, the bitcell is written to the high-state by tunneling electrons from the channel to ...

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Reliability Of Nand Flash Memory

Aritome¹

2015

Nand Flash Memory Technologies

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A novel cell structure suitable for a 3 volt operation, sector erase flash memory

Cited by 26 publications

References 4 publications

Flash memory cells-an overview

Flash memory cells-an overview

An advanced flash memory technology on SOI

Reliability Of Nand Flash Memory

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