A novel clock distribution and dynamic de-skewing methodology

Proceedings of the 46th Annual Design Automation Conference

2009

We present an unconventional clock distribution that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular standard cell approach that compensates intra-die temperature and process variances. Our clock distribution provides control over regional clock skew, permits use in beneficial skew applications and facilitates silicon-debug. By adding routing to the serial clock network, we permit post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability to the network.

“…This averaging technique was first proposed by Grover et al [2] and has been used in [3,4]. Our clock network is the first to use it to mitigate mismatch effects in a clock network.…”

Section: Serial Clock Networkmentioning

confidence: 99%

Serial reconfigurable mismatch-tolerant clock distribution

Proceedings of the 46th Annual Design Automation Conference

2009

“…Clock distribution represents an increasingly difficult challenge due to progressively more complex systems, decreased power supply voltages, larger die sizes and higher clock frequencies [1,2]. There are a number of sometimes conflicting characteristics that need to be balanced to create an adequate clock distribution network (CDN).…”

Section: Introductionmentioning

confidence: 99%

Reference-Based Clock Distribution Architectures

2006 49th IEEE International Midwest Symposium on Circuits and Systems

2006

Abstract-This paper examines the use of clock distribution architectures employing a reference-based skew compensation technique. For each clock domain, a bi-directional clock line is daisy-chained using specially designed switches at each tap in the distribution. Daisy-chaining the clock decreases the clock load by eliminating the redundant paths used to equalize delays in traditional H-tree distributions. Clock skew is accounted for by actively synchronizing each local clock to a position directly between forward and reverse-moving reference clocks. This reference-based clocking strategy achieves a set of skew-tolerant clocks at each tap in a daisychain. The design provides simple-to-layout and scalable multipoint skew compensation useful for large designs. The implementation of a reference-based clocking chain is outlined, followed by the description of single clock and multi-clock architectures using this design strategy.

“…Traditional H-trees are not well-suited to distributing clocks to asymmetric, irregularly shaped clock domains and add further complication to the floorplanning and layout of designs. The schemes that apply skew reduction techniques on existing H-tree distributions [2], [9], [10] suffer from the same drawbacks of their forbearers: high power consumption and inefficient use of interconnect. Other distributions perform skew compensation at the source, independently for each leaf [2], [6], [11].…”

Section: Introductionmentioning

confidence: 99%

“…The schemes that apply skew reduction techniques on existing H-tree distributions [2], [9], [10] suffer from the same drawbacks of their forbearers: high power consumption and inefficient use of interconnect. Other distributions perform skew compensation at the source, independently for each leaf [2], [6], [11]. This creates a need for long and varying length reference lines returning from each leaf to the source, introducing errors to the skew compensation technique due to the process-dependant delay of each feedback line [12].…”

Section: Introductionmentioning

confidence: 99%

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Reconfigurable Clock Distribution Circuitry

2007 IEEE International Symposium on Circuits and Systems

2007

Abstract-We present the circuitry required for implementing a multi-clock reconfigurable, reprogrammable clock distribution network for integrated circuits using a reference-based scheme for skew compensation. In the scheme, a device is subdivided into multiple regions and a bi-directional clock distribution line is daisy-chained through the device, connecting each region in the domain. Switching structures that can be used to re-route the clock chain are added where needed. The proposed design simplifies layout for irregularly shaped clock domains and provides flexibility to designers by enabling post-fabrication changes to the clock distribution network. Reconfigurable clock distribution networks can be used in some ASICs, SoCs and FPGAs. The reference-based approach used is applicable to both single and multiple clock distributions.