A Novel Cu Electrical Fuse Structure and Blowing Scheme Utilizing Crack-Assisted Mode for 90-45nm-Node and Beyond

Ueda, T.; Takaoka, H.; Hamada, Mototsugu; Kobayashi, Yuichi; Ono, Akemi

doi:10.1109/vlsit.2006.1705255

Cited by 16 publications

(9 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There are three kinds of e-fuse devices: (i) formed with a silicide gate poly-Si electrode material (gate-electrode-fuse); (ii) constructed from Cu wire (Cu-fuse); (iii) consisting of a Cu-via (via-fuse) [45][46][47]. When we consider future device scaling, the gate-electrode-fuse may be problematic.…”

Section: Introductionmentioning

confidence: 99%

Testing of Interposer-Based 2.5D Integrated Circuits

Wang

Chakrabarty

2017

View full text Add to dashboard Cite

show abstract

Section: Introductionmentioning

confidence: 99%

Testing of Interposer-Based 2.5D Integrated Circuits

Wang

Chakrabarty

2017

View full text Add to dashboard Cite

show abstract

“…An efuse-type memory uses an efuse as its memory element. Since the process technology of the efuse is shrunk down, the silicide material deposited on the poly-Si is changed to tungsten silicide [3], titanium silicide [4], cobalt silicide [5], copper silicide [6], and nickel silicide [7]. There are a single ended bit line (BL) sensing scheme and a double ended BL sensing scheme as BL sensing schemes [8].…”

Section: Introductionmentioning

confidence: 99%

Design of 1 kbit antifuse one time programmable memory IP using dual program voltage

Jin

Jang

Kim

et al. 2011

J. Cent. South Univ. Technol.

View full text Add to dashboard Cite

A 1 kbit antifuse one time programmable (OTP) memory IP, which is one of the non-volatile memory IPs, was designed and used for power management integrated circuits (ICs). A conventional antifuse OTP cell using a single positive program voltage (V PP ) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time, securing the reliability of medium voltage (V M ) devices that are thick gate transistors. A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield drop. For the newly proposed cell, a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the antifuse. The layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek's 0.18 µm Bipolar-CMOS-DMOS (BCD) process is 567.9 μm×205.135 µm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.

show abstract

“…E-fuse is an electrically programmable memory element and is widely applied to: (1) replace a defective element with a redundant element, (2) write Chip ID (electrical chip identification: ECID) and (3) various security code storage, trim element for circuit performances. A typical implementation is a poly (or Cu) fuse, where Joule heating is used to melt metal link and resulting resistance change is sensed by using a latch as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…A typical implementation is a poly (or Cu) fuse, where Joule heating is used to melt metal link and resulting resistance change is sensed by using a latch as shown in Fig. 1a [1][2][3][4][5][6][7][8][9][10][11]. Anti-fuse is one of the candidates for e-fuse [12][13][14].…”

Section: Introductionmentioning

confidence: 99%