A Novel Design and Implementation of 8-Bit and 16-Bit Hybrid ALU

Shirol, Suhas B.; Ramakrishna, S.; Shettar, Rajashekar B.

doi:10.1007/978-3-030-16657-1_4

Cited by 2 publications

(3 citation statements)

References 10 publications

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“…3) After completing the 8-bit ALU, a new problem is how to change the 8-bit ALU to 64-bit ALU. After thinking and in-depth learning, the following methods are summarized Changing an 8-bit ALU to a 64-bit ALU requires the following steps [10]: Expand bit width: Expand each bit width in the ALU to 64 bits. This by copying and filling "0", ensuring that each operand and result has 64 bits.…”

Section: Simulation Waveformmentioning

confidence: 99%

“…Through repeated modification and compilation, they can be successfully compiled.3) After completing the 8-bit ALU, a new problem is how to change the 8-bit ALU to 64-bit ALU. After thinking and in-depth learning, the following methods are summarized Changing an 8-bit ALU to a 64-bit ALU requires the following steps[10]: Expand bit width: Expand each bit width in the ALU to 64 bits. This by copying and filling "0", ensuring that each operand and result has 64 bits.Expansion control signal: Due to the change of bit width, the control signal of ALU also needs to be expanded accordingly.…”

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confidence: 99%

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Design and implementation of an 8-bit ALU based on verilog HDL

Huang

2023

TNS

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Many modern processors incorporate an Arithmetic Logic Unit (ALU) as an integral component. The ALU plays a pivotal role in arithmetic and logical operations, making it a fundamental block in processor architecture. Utilizing software tools like Quartus II and ModelSim, one can seamlessly design, implement, and simulate an 8-bit ALU. This research focuses on creating an ALU that can perform a broad range of operations, including Addition, Subtraction, Multiplication, Division, Shifting, Rotation, AND, OR, XOR, NOR, NAND, XNOR, and Comparison. With these 16 operations in mind, the ALUs circuitry was meticulously crafted using Quartus II. To validate its functionality and performance, joint simulations were conducted with both Quartus II and ModelSim. As a result, comprehensive simulation waveforms were derived, offering insights into the ALUs behavior and response for each instruction. These waveforms serve as a testament to the ALUs robust design and provide a foundation for further analysis and optimization.

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Section: Simulation Waveformmentioning

confidence: 99%

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confidence: 99%

Design and implementation of an 8-bit ALU based on verilog HDL

Huang

2023

TNS

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“…Power dissipation is a major issue in low-power digital VLSI design, and reverse logic is the answer. Because of this, ALUs use reversible and irreversible logic gates to reduce latency and power consumption[Shirol et al (2018)]. Multiplication is critical in high-end processors since it determines the processor's capability.…”

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confidence: 99%

Design of a Novel Arithmetic Architecture Using Hybrid Vedic Sutras in Digital Signal Processing Applications

RAMAMOORTHY,

PERIASAMY

2023

Preprint

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Digital signal processing (DSP) is a vast and active field of research. High throughput is required for most wireless communication systems. The Fast Fourier Transform (FFT), which lies at the heart of most modulators, is a major stumbling block to communication.The intrinsic floating-point multiplier units located within the butterfly units of every FFT execute these calculations. The performance of FFT in terms of throughput is limited by multiplication. As a result, Multiplier topologies with reduced truncation errors are needed for high-speed, low-power systems. This paper presents high-performance FFT units for DSP processor cores based on hybrid Vedic multiplier units. The Vedic multiplier that has been presented is based on the Vedic multiplication sutras. In the decimal number system, these sutras have historically been employed to multiply two numbers. In this study, a hybrid Vedic multiplier based on Indian Vedic mathematics' Urdhva-Tiryagbhyam and Nikhilam navatascaramam sutra is suggested. An efficient multiplier is the fundamental goal of this study, which aims to minimize the size and delay path of a multiplier while enhancing the performance of the processor. Verilog HDL was used to implement the complete design. Xilinx ISE Design Suite 14.5, which is used for synthesis and simulations, was used. It is matched to previously reported Vedic multiplier designs in terms of speed and area consumed. It features a speedier development process and a lower computation complexity than the traditional multiplier.

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A Novel Design and Implementation of 8-Bit and 16-Bit Hybrid ALU

Cited by 2 publications

References 10 publications

Design and implementation of an 8-bit ALU based on verilog HDL

Design and implementation of an 8-bit ALU based on verilog HDL

Design of a Novel Arithmetic Architecture Using Hybrid Vedic Sutras in Digital Signal Processing Applications

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