A Novel Design Flow for a Security-Driven Synthesis of Side-Channel Hardened Cryptographic Modules

Abstract

Abstract:Over the last few decades, computer-aided engineering (CAE) tools have been developed and improved in order to ensure a short time-to-market in the chip design business. Up to now, these design tools do not yet support an integrated design strategy for the development of side-channel-resistant hardware implementations. In order to close this gap, a novel framework named AMASIVE (Adaptable Modular Autonomous SIde-Channel Vulnerability Evaluator) was developed. It supports the designer in implementing devices hardened against power attacks by exploiting novel security-driven synthesis methods. The article at hand can be seen as the second of the two contributions that address the AMASIVE framework. While the first one describes how the framework automatically detects vulnerabilities against power attacks, the second one explains how a design can be hardened in an automatic way by means of appropriate countermeasures, which are tailored to the identified weaknesses. In addition to the theoretical introduction of the fundamental concepts, we demonstrate an application to the hardening of a complete hardware implementation of the block cipher PRESENT.

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level

“…Apart from power side-channel attacks and their corresponding countermeasures, another highly important topic in this domain is power side-channel leakage assessment. Several techniques have been proposed in this domain including signalto-noise ratio (SNR) [7], Test Vector Leakage Assessment (TVLA) methodology [8], success rate [9], and autonomous side-channel vulnerability evaluator (AMASIVE) [10], [11]. However, these techniques suffer from the following major limitations.…”