A Novel Design for Computation of All Transforms in H.264/AVC Decoders

A high-throughput ASIC processor for 8×8 transform coding in H.264/AVC

“…It uses two 1D DCT processors and transpose RAM with a latency of 144 clock cycles. The high-throughput and cost-effective implementation of six different integer transforms is proposed in [11]. This implementation maximizes the shared hardware and it is able to process 64 input pixels in a two-stage pipelined architecture for computing the direct 8 Â 8 transform or two 4 Â 4 transforms in parallel.…”

“…Table 5 shows the characteristics and the performances of previously published ASIC implementations for comparison purposes, although some of them only implement parts of the H.264/AVC transform coding process. Thus, processors in [6][7][8][9][10][11][12] exclusively implement the transform (forward and/or inverse). In [21] only the forward transform and quantization is considered, while the processors in [13,14] perform the complete transform and coding process.…”

“…An interesting high-throughput and cost-effective implementation of six different integer transforms based on a shared hardware is described in [10]. For a high profile decoder, a flexible architecture for computing all inverse transforms is presented in [11]. With a more general purpose outlook, a unique kernel for multi-standard video MPEG and H.264 applications is described in [12].…”

Variable Bit-Depth Processor for 8×8 Transform and Quantization Coding in H.264/AVC

“…This implementation maximizes the shared hardware and it is able to process 64 input pixels in a two-stage pipelined architecture to compute the direct 8×8 transform or two 4×4 transforms in parallel. Another flexible architecture is presented in (Chao at al., 2007), which is suitable for a H.264 high profile decoder capable of processing a macroblock in 95 clock cycles with the 8×8 inverse transform or only 54 clock cycles without it. The architecture described in (Lee & Cho, 2008) and quantization for unified standard video CODEC (JPEG, MPEG-1/2/4, H.264 and VC-1).…”

“…In order to reduce hardware, diverse configurable data-path architectures to support all of these transforms in a unified scheme have been proposed. Other examples of this kind of architectures include; the multi-transform processor where the quantization is performed at the pace demanded by the entropy coder in (Bruguera & Osorio, 2006), the low hardware cost suitable for VLSI implementations in (Fan, 2006), the reduced hardware and high latency in (Chao et al, 2007), the high-performance architecture for high-definition applications in ( Ma & et. al, 2007), the IP design to be implemented on an ASIP-controlled SoC platform in (Ngo et al, 2008), the high-performance, low-power unified transform architecture in (Choi et al, 2008), the highly parallel joint circuit architecture in , and the fast, high-throughput and cost-effective implementation in (Hwangbo & Kyung, 2010).…”