2018
DOI: 10.1016/j.vlsi.2017.09.002
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A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power

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Cited by 24 publications
(15 citation statements)
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“…As we have proposed SRs out of DFF, we have taken similar low-power DFFs for building register designs. They are named as follows: transmission gate SR developed from a conventional transmission gate FF (TGSR) (Zhang et al , 2011); topologically compressed SR made out of topologically compressed FF (TCSR) (Kawai et al , 2014); logic structure reduction technique SR developed from logic structure reduction technique FF (LRSR) (Lin et al , 2017); SR made from a dynamic FF designed by author Gago (GagoSR) (Gago et al , 1993); pulse-triggered SR from pulse-triggered FF (PTSR) (Karimi et al , 2018); lector-based clock gating SR developed from LBCG FF (LBCG-SR) (Bhattacharjee and Majumder, 2018); scan SR developed from Scan FF (SC-SR) (Razmdideh et al , 2015); 18 transistor SRs made from 18TFF (18TSR) (Cai et al , 2018); and implicit pulse-triggered FF with clock gating and pull-up control scheme SR developed from IP-CGPC FF (IP-CGPCSR) (Geng et al , 2016). …”
Section: Resultsmentioning
confidence: 99%
“…As we have proposed SRs out of DFF, we have taken similar low-power DFFs for building register designs. They are named as follows: transmission gate SR developed from a conventional transmission gate FF (TGSR) (Zhang et al , 2011); topologically compressed SR made out of topologically compressed FF (TCSR) (Kawai et al , 2014); logic structure reduction technique SR developed from logic structure reduction technique FF (LRSR) (Lin et al , 2017); SR made from a dynamic FF designed by author Gago (GagoSR) (Gago et al , 1993); pulse-triggered SR from pulse-triggered FF (PTSR) (Karimi et al , 2018); lector-based clock gating SR developed from LBCG FF (LBCG-SR) (Bhattacharjee and Majumder, 2018); scan SR developed from Scan FF (SC-SR) (Razmdideh et al , 2015); 18 transistor SRs made from 18TFF (18TSR) (Cai et al , 2018); and implicit pulse-triggered FF with clock gating and pull-up control scheme SR developed from IP-CGPC FF (IP-CGPCSR) (Geng et al , 2016). …”
Section: Resultsmentioning
confidence: 99%
“…Redundant formation of hardened designs often causes high overheads. Pulse-Triggered Flip-Flop (PFF) is an option to help in penalty reducing or area diminishing due to its simple and compact structure [17,18]. However, high power consumption due to redundant switching activities and contention mechanism is usually an issue [14,19,20,21].…”
Section: Introductionmentioning
confidence: 99%
“…According to Moore's law, it is anticipated that the number of transistors on a chip doubles every 2 years [1]. However, traditional CMOS technology is facing a variety of challenges, in which limitations of the CMOS technology require looking for other technologies to overcome these limitations [2].…”
Section: Introductionmentioning
confidence: 99%