A Novel Design in Formal Verification Corresponding to Mixed Signals by Differential Learning

Vidhya, D.; Ramachandra, Manjunath

doi:10.1007/978-3-319-57141-6_40

Cited by 2 publications

(3 citation statements)

References 11 publications

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“…This work has contributed to the work of the Accellera committee standardizing Verilog-AMS. Several other methods have also been proposed to address AMS system veriication [9,62,78,107]. In this paper, we primarily focus on the assertion-based validation of digital systems.…”

Section: Design Interfacementioning

confidence: 99%

A Survey on Assertion-based Hardware Verification

et al. 2022

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Hardware verification of modern electronic systems has been identified as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware verification is to drastically reduce the validation and debug time without sacrificing the design quality. Assertion-based verification is a promising avenue for efficient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware verification. Specifically, we outline how to define assertions using temporal logic to specify expected behaviors in different abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements.

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Section: Design Interfacementioning

confidence: 99%

A Survey on Assertion-based Hardware Verification

et al. 2022

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“…The verification is performed at different levels and different modes. A framework based on differential learning approach to performing the formal verification is presented in Vidya [11] by considering mixed signals. The technique has presented an analytical modeling approach that considers an algorithm to generate the multiple mixed signals meant for a feasible operation of the mixed signal circuits, an algorithm for training and verification.…”

Section: Introductionmentioning

confidence: 99%

“…The technique has presented an analytical modeling approach that considers an algorithm to generate the multiple mixed signals meant for a feasible operation of the mixed signal circuits, an algorithm for training and verification. From outcomes analysis, it was found that [11] achieved 98.7% accuracy with the better speed of response than other machine learning algorithms.The work of Chitti et al [12], presented a unique test model for different SoCs in which Cadence verification methodology is adopted for the SoC environment. From the outcome analysis [12] found an effective reduction in simulation time of SoC with respect to other existing works.…”

Section: Introductionmentioning

confidence: 99%

An optimized method towards formal verification of mixed signals using differential fed neural network over FFNN

Vidya¹,

Ramachandra²

2019

IJECE

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<span lang="EN-US">Today, the semiconductor industries are rapidly usinganalog and mixed signals to achieve cost-effective solutions on a System on Chip (SoC) design. The SoC device is a part of analog, digital and essential mixed-signal models/circuits merged on a semiconductor device, which provides the platform to build modern retail/consumer electronics appliances with smart technology. In order to evaluate the mixed signals, the conventional approaches are not effective with respect to its performance, time and manufacturing cost. Thus, the recent researches were much interested in formal verification technique as it provides the evidence of conscious algorithms in a system. The demand for formal verification in the SoC designs in the context of software and hardware platform is high because of its cost and accuracy. Thus, the paper introduces atechnique of formal verification for mixed signals by using training models of the Differential fed neural network (DFNN) over feedforward neural network (FFNN). The formal verification is performed through equivalence checking by using recently adopted designs as reference designs. The outcomes of the verification techniques suggests that DFNN based technique improves the training accuracy and optimizes the hardware resources like area, power than the FFNN based technique.</span>

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A Novel Design in Formal Verification Corresponding to Mixed Signals by Differential Learning

Cited by 2 publications

References 11 publications

A Survey on Assertion-based Hardware Verification

A Survey on Assertion-based Hardware Verification

An optimized method towards formal verification of mixed signals using differential fed neural network over FFNN

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