A novel design methodology for low-noise and high-gain transimpedance amplifiers

Abstract

This paper reports on design and measurement results of a state of the art low-noise and high-gain transimpedance amplifier (TIA) implemented in 0.18 μm TSMC CMOS technology. Thorough design methodology for high gain and low power TIA design for 2.5 Gb/s optical communication circuits family is presented. A noiseless capacitive feedback is proposed and implemented as a noise efficient feedback network for TIA circuits. Besides, analytical noise calculations in this family of TIA circuits are presented and optimum noise criteria are derived. The saturation and instability problem of TIA circuits resulted from DC dark current of the input photodiodes (PDs) is addressed and a circuit level solution is presented. The measurement results of 0.18 μm chip shows bandwidth of 52 kHz to 1.62 GHz, and transimpedance gain of 75.5 dB while dissipating 26.3 mW from a 2.2 V power supply, including the output buffer. Taking advantage of proposed capacitive feedback network and optimum noise criteria, noise measurement results show average input referred current noise of 3.18 pA/Hz for this TIA in the bandwidth of operation. Index Terms-Current-input circuits, low-noise circuits, optical communications, transimpedance amplifiers I. INTRODUCTIONECENTLY, transimpedance amplifiers are being used in a very wide range of applications such as optical communications (families of 2.5, 10, 25,... Gb/s), mechanical sensors, biosensors, and other specific bio-applications like DNA sequencing, and impedance spectroscopy [1][2][3][4]. This broad range of applications results in different sets of constrains for a circuit designer when designing a TIA. While in high speed families of optical communication circuits the main goal is pushing the bandwidth of TIA higher in GHz range [4], bio-application TIAs usually stay in much lower frequency ranges but at the same time demand better noise performances and lower power consumption for chronic/long-term implantable versions [1][2][3]. So, the first question to be addressed in a TIA design is which application

A design methodology for programmable-gain low-noise TIA in CMOS

“…Note that the detailed model from above does not contain C C nor includes the impact of the bias resistors R bias,1 and R bias,2 . Figure 7 compares the simplified constant gain model against the model of Shahdoost [20] and the model suggested in this work.…”

“…Furthermore, the design clearly tradeoffs among the key TIA parameters such as noise, gain and bandwidth. On the other hand, the feedback approach itself has important structural benefits as it ensures almost constant transimpedance gain in the bandwidth of interest while decreasing the sensitivity to process and temperature variations [20]. Thus, it may be beneficial to keep the general feedback structure of the amplifier, while substituting the noisy feedback resistor with a less noisy or Fig.…”

A Review of Modern CMOS Transimpedance Amplifiers for OTDR Applications

“…However, several issues must be addressed for the circuit to fit the specifications. For example, in his early works [31,40] the author did not consider the flatness within the passband (reported peaking in the frequency response less around 1.0-1.5 dB) which may still lead to unacceptable signal distortion in OTDR applications. Furthermore, the series of works of Shahdoost did not report on the input parasitic capacitance nor the value of C D .…”

“…An attempt to address the typical problems of CG and SFB TIA by designing a so-called capacitive-feedback (CF) TIA have been first reported in the seminal work of Razavi [33]. Later, in a series of works Shahdoost elaborated the concept of the capacitive feedback [21,31,32,40]. The general circuit topology of a TIA with a capacitive-feedback network is shown in Figure 7.…”

“…In the case of the CS input stage (transistor M 1 and resistor R 1 ), the noise calculations can be shown [40] to result in:…”