“…Simply, M i can be realized by an NMOS transistor with associated switch closed on phase ϕ i [10], the so-called second generation SI memory cell. But, for cancelling non-ideal behaviour, several enhancement techniques such as cascode and S 2 I can be used [10][11][12][13][14][15][16]. Particularly, when S 2 I technique is selected to realize M i and J, Fig.1(a) can be specialized to the structure used in [17,18].…”