2021 2nd Global Conference for Advancement in Technology (GCAT) 2021
DOI: 10.1109/gcat52182.2021.9587599
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A Novel design of SOI based Fin Gate TFET

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Cited by 8 publications
(2 citation statements)
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“…It eliminates the need for a p-n junction, making the junction-less fin gate TFET highly scalable and simple to construct. A p-i-n junction channel design is used in the fundamental building blocks of a TFET [6]. The primary TFET device, as shown in figure 1, features a p-type source and an n-type drain.…”
Section: ░ 1 Introductionmentioning
confidence: 99%
“…It eliminates the need for a p-n junction, making the junction-less fin gate TFET highly scalable and simple to construct. A p-i-n junction channel design is used in the fundamental building blocks of a TFET [6]. The primary TFET device, as shown in figure 1, features a p-type source and an n-type drain.…”
Section: ░ 1 Introductionmentioning
confidence: 99%
“…The rate of BTBT generation that occurs in a large (line) tunnelling region from the gate overlap source section to the channel junction is referred to as "line tunnelling" The key benefit is that LTFETs provide more tunnelling current. It was suggested that using LTFETs might increase device performance [8].…”
mentioning
confidence: 99%