A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

Abstract

For the design of inverter-based OTAs with differential input and single-ended output, the differential to single-ended (D2S) converter is a key building block. In fact, the performance of the D2S strongly affects the overall common-mode rejection ratio (CMRR) and input common-mode range (ICMR) of the whole OTA. In recent literature, inverter-based OTAs rely on a D2S topology based on an inverter driving another inverter with the input and output tight together which behaves as a "diode" connected device to implement a voltage gain approximately equal to −1. However, since this approach is based on the matching of the inverters, the performance of this D2S results sensitive to PVT variations if the bias point of the inverters is not properly stabilized. In this paper we present a novel topology of inverterbased D2S converter, exploiting an auxiliary, standard-cell-based, error amplifier and a local feedback loop. The proposed D2S, compared to the conventional one, exhibits higher CMRR, improved ICMR and better robustness with respect to PVT variations. We present also an ULV, standard-cell-based OTA, which exploits the proposed D2S converter and shows excellent performance figures of merit with low area footprint.

A Novel High Performance Standard-Cell Based ULV OTA Exploiting an Improved Basic Amplifier

“…6. The first stage is a differential to single ended converter (D2S), which has been implemented according to the topology presented in [67] and depicted in Fig. 7.…”

“…This architecture is therefore a three stage OTA whose gain is typically higher than 60dB. In fact [67].…”

“…In [55] a method has been proposed to center the dynamic-range of these inverters, making them more robust against PVT variations. In addition, novel topologies for differential to single-ended converters have been proposed [67] to improve common-mode rejection ratio and input common-mode range of standard-cell-based OTAs.…”

A 0.3 V OTA with Enhanced CMRR and High Robustness to PVT Variations

“…Solution based on a fully-digital approach (DIGOTA) [22][23][24] or operating in the time domain [25,26] have been proposed, but most of these techniques exploit analog approaches such as body-driving [27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45], floating-gate [46] and floating-body [47] devices, and inverter-based architectures [48][49][50][51]. The latter are often suitable for implementation using digital standard-cell libraries [52][53][54][55], thus simplifying the layout through the use of automatic place-and-route CAD tools and easing design portability among different technologies.…”

“…A commonmode feedforward (CMFF) approach [29,38,[56][57][58] can be used to improve CMRR in typical conditions, also reducing variability under PVT. In [43], an improved body-driven current mirror was proposed and applied to a ULV differential-to-single-ended (D2S) converter stage to improve its CMRR; a similar idea was applied in [53] to achieve high CMRR in a standard-cell-based OTA. The idea was to exploit an auxiliary amplifier to attenuate the gain error of the current mirror.…”