A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device

Seo, Sang‐Hun; Yang, Wonyoung; Lee, Han-Sin; Kim, Moo-Sung; Koh, K.; Park, Seung-Hyun; Kim, Kyeong-Tae

doi:10.1109/led.2002.805769

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A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device

Cited by 3 publications

References 4 publications

Optimization of 1KByte 6T SRAM using block partitioning method and gated Vdd concept

Optimization of 1KByte 6T SRAM using block partitioning method and gated Vdd concept

Employing work function enginnering and asymmetric gate oxide in nano-scale source-heterojunction-MOS-transistor

Effects of gate notching profile defect on performance characteristics of short-channel NMOSFET with channel length of 0.12 μm

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