A novel dual-feed low-dropout regulator

Abstract

A novel dual-feed (DF) low-dropout (LDO) is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO. In addition, the transient performance is optimized by adjusting the damping ratio and natural frequency. With a 1 μF decoupling capacitor, the proposed DF-LDO is fabricated in a 0.18 μm CMOS process and its output voltage is 1.5 V. When the workload changes from 100 μA to 100 mA in 100 ns, load regulation of 7 mV for a 100 mA step is achieved, the settling time is 997 ns and the undershoot is 12.8 mV; when the workload changes from 100 mA to 100 μA in 100 ns, the settling time is 249 ns with an imperceptible overshoot.

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

“…Several methods have been proposed to solve the above problems [4][5][6][7][8][9][10][11][12][13][14][15][16][17] . The LDO regulator [4] uses a digital error amplifier which consumes only 103 nA quiescent current, but it is reported that the settling time is as long as 400 μs.…”

“…The LDO regulator [4] uses a digital error amplifier which consumes only 103 nA quiescent current, but it is reported that the settling time is as long as 400 μs. A dynamic bias-current boost technology [6] is used to realize the ultra-low power design, which achieves only 1.2 μA quiescent current, but it has a large undershoot and overshoot, which makes it im-practical in some applications. Based on a flipped voltage follower, a simple folding structure of LDO circuit [8] is proposed.…”