A novel dual-loop multi-phase frequency synthesizer

Ye, Zhipeng; Chen, Wenbin; Kennedy, Michael Peter

doi:10.1109/ecctd.2007.4529659

Cited by 1 publication

(3 citation statements)

References 11 publications

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“…Where r=1+G 2 /G 1 , and (1), (2) and (3) is for the CDTL; the region enclosed by (1), (2) and (4) is for the TDTL when Ψ 0 =π⁄2; and the region enclosed by (1) and (5) is for the TDTL when Ψ 0 =π. …”

Section: Tdtl System Architecture and Modelmentioning

confidence: 99%

“…A phase lag ωτ ψ = is induced to the input signal after it passes through the time delay block. Therefore, x(t) is generated, which is a phase shifted version of the input signal y(t), this signal is given by (2).…”

Section: Tdtl System Architecture and Modelmentioning

confidence: 99%

“…The frequencies produced are basically a multiple, either integer or fractional, of the reference frequency. Producing the required frequency in the case of multi-standard wireless systems enables the correct demodulation of the received signal [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

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Comparison of various order TDTL frequency synthesizers

et al. 2008

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This paper compares the performance of first and second order time delay tanlock loop (TDTL) based integer frequency synthesizers. Varying the order of the loop changes the locking region of the complete system and affects the locking convergence. The synthesizer divider block also affects the system stability. Depending on the division factor the system may be driven outside its locking region. This is overcome by introducing an additional block that adaptively stabilizes the loop by driving it back to within the locking region. The results achieved indicate that the adaptive integer frequency synthesizers operate satisfactorily. The second order loop has shown to give a better acquisition performance when compared with the first order loop. This is due to the zero steady state phase error exhibited by the loop.

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Section: Tdtl System Architecture and Modelmentioning

confidence: 99%

Section: Tdtl System Architecture and Modelmentioning

confidence: 99%