A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients Signals

Rad, Reza M.; Plusquellic, Jim

doi:10.1007/s10836-008-5092-0

Cited by 6 publications

(2 citation statements)

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“…Therefore, we need a scaling technique to redistrib ute the currents obtained using 1 Q simulations over all the power pads in case of 4Q and 9Q. In [5][6], the authors propose signal calibration techniques to com pensate for process and environment variations in a CUT. Both DC and AC techniques are investigated and their effectiveness compared against a no-signal-calibra tion technique.…”

Section: Signal Scaling Techniquementioning

confidence: 99%

“…Circuit with Input Current Source and Relative Voltage Drops[5] 2.3 Computation of Voltage DropSelf drop is the drop in voltage due to the transient current of the individual switching gates. To compute the self drops on the gates in a switching path, the C2V impulse responses obtained during the power grid char acterization are convolved with the current transients of the gates on the switching paths.…”

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confidence: 99%

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Estimating Power Supply Noise and its impact on path delay

Rao

Sathyanarayana

Kallianpur

et al. 2012

2012 IEEE 30th VLSI Test Symposium (VTS)

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Power Supply Noise has a significant impact on path delay and therefore its estimation is critical in delay testing. In deep sub-micron technologies, voltages are scaled and the number of switching gates has increased which make chips susceptible to power supply noise. Running full-chip simulations on large designs to pre dict the noise is time consuming and expensive. There fore, most existing techniques are based on statistical approaches. In this paper, we propose a current-based dynamic method to estimate power supply noise and use the framework to predict the increase in path delay caused by the variations in power supply voltage with out carrying out a full-chip simulation. A convolu tion-based technique is used to compute the path delays where standalone paths are extracted and simulated. Experimental results reported for estimating noise using the ISCAS-85 benchmark circuit are within 10% of full-chip results. The delay predictions carried out on two other experimental designs using our technique closely match full-chip results with a maximum error of 2%.

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Section: Signal Scaling Techniquementioning

confidence: 99%

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confidence: 99%