A novel fault tolerant majority gate in quantum-dot cellular automata to create a revolution in design of fault tolerant nanostructures, with physical verification

Hosseinzadeh, Hassan; Heikalabad, Saeed Rasouli

doi:10.1016/j.mee.2018.01.019

Cited by 44 publications

(26 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, in comparison with the least fault‐tolerant majority gate by Sen et al at three different levels of 0.5 Ek, 1 Ek, and 1.5 Ek, and 45.67%, 40.60% and 7.54% reductions in energy consumption are observed, respectively. In addition, the proposed majority gate shows more than 34% tolerance to double‐cell omission defect in comparison with the best previous fault‐tolerant majority gate by Hosseinzadeh and Heikalabad . Furthermore, Figure A to N shows the percentage of improvements of the proposed fault‐tolerant structure in comparison with previous works.…”

Section: The Proposed Fault‐tolerant Circuitsmentioning

confidence: 80%

“…In addition, Table illustrates the performance of the proposed fault‐tolerant full adder in comparison to other fault‐tolerant full adder in previous studies . As can be seen from Table , the proposed fault‐tolerant full adder is superior to previous designs in terms of fault tolerance, which shows an improvement of more than 15% compared to the best design in the work of Sen et al…”

Section: The Proposed Fault‐tolerant Circuitsmentioning

confidence: 83%

“…The energy dissipation thermal display of the proposed fault‐tolerant structure and existing fault‐tolerant three‐input majority gates in previous studies are illustrated in Figure . As can be seen in Figure , it should be noted that high‐power cells generate a lot of heat in which hot spots appear in darker colors.…”

Section: The Proposed Fault‐tolerant Circuitsmentioning

confidence: 99%

“…The energy dissipation thermal for the QCA majority cells (at 2° Ek) with 0.5 Ek. A, Design of Huang et al; B, Design of Du et al; C, Design of Sen et al; D, Design of Sen et al; E, design; F, Design of Kumar and Mitra; G, Design of Sun et al; H, Design of Farazkish; I, Design 1 of Ahmadpour and Mosleh; J, Design 2 of Ahmadpour and Mosleh; K, Design of Moghimizadeh and Mosleh; L, Proposed design…”

Section: The Proposed Fault‐tolerant Circuitsmentioning

confidence: 99%

“…Hosseinzadeh and Heikalabad have presented a fault‐tolerant three‐input majority gate with 16 total cells, which has 100% and 54% tolerance against single‐cell and double‐cell defects, respectively. Moreover, it uses one clock phase.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A novel ultra‐dense and low‐power structure for fault‐tolerant three‐input majority gate in QCA technology

Ahmadpour

Mosleh

2019

Concurrency and Computation

View full text Add to dashboard Cite

Quantum-dot cellular automata (QCA) is a very interesting nanoscale technology. Ultradense structure and ultralow power consumption are the most important features of QCA compared to CMOS. QCA circuits often suffer from various types of manufacturing defects and are therefore prone to fault. Hence, the design of fault-tolerant circuits in QCA technology is considered a necessity. In this paper, a novel fault-tolerant three-input majority gate is presented using 12 simple and rotated cells in QCA technology. The proposed structure is investigated against all kinds of cell omission, extra-cell deposition, and cell displacement defects. The simulation results are verified by QCADesigner 2.0.3, and it showed 100%, 89.29%, and 100% tolerance against single-cell omission, double-cell omission, and extra-cell deposition, respectively. In addition, the proposed structure is robust against cell displacement defects. Finally, using the proposed structure, a novel coplanar full adder is presented. The results were compared and indicated that the proposed designs are more reliable than the existing designs. Furthermore, QCAPro power estimator tool was employed to estimate the energy dissipation of the proposed structure. KEYWORDSfault-tolerant, nanotechnology, quantum-dot cellular automata (QCA), three-input majority gate INTRODUCTIONIn the near future, complementary metal-oxide-semiconductor (CMOS) technology is expected to reach the end of its way due to limitations such as switching speed, scaling specifications, high cost of lithography, and thermal challenges. 1-3 CMOS technology also suffers from lower tolerability and manufacturing diversity, which have a negative impact on the reliability of these devices, leading to an increase in the number of faults. Future CMOS constraints have led many researchers to design nanoscale devices. 4 Quantum-dot cellular automata (QCA) has appeared as a favorable new innovation for future integrated circuit generation, which can overcome CMOS constraints. 3 The simplest element in QCA technology is a square cell with four quantum dots located in its four corners. The transfer of information takes place by columbic interactions between the fundamental elements (cells) instead of electrical current. [3][4][5] Up to now, extensive attempts have been made on the design of various digital circuits such as multipliers, 6-8 adders, 9-19 memory devices, 20-23 arithmetic and logic unit, 24 and multiplexers [25][26][27][28][29] in QCA technology, but according to a conducted study by Bahar et al, 30 the high complexity of nanocircuit structures results in the need to design high fault-tolerant structures. The QCA technology encounters with a variety of manufacturing defects such as extra-cell deposition, cell omission, cell displacement, or cell misalignment that make QCA circuits unusable. 31,32 A three-input majority gate is considered one of the main basic gate in the QCA circuits. 33,34 Providing robust structures for the majority gate will result in the creation of fault-tolerant logic cir...

show abstract

Section: The Proposed Fault‐tolerant Circuitsmentioning

confidence: 80%

Section: The Proposed Fault‐tolerant Circuitsmentioning

confidence: 83%

Section: The Proposed Fault‐tolerant Circuitsmentioning

confidence: 99%

Section: The Proposed Fault‐tolerant Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A novel ultra‐dense and low‐power structure for fault‐tolerant three‐input majority gate in QCA technology

Ahmadpour

Mosleh

2019

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

References

2024

Computing With Multi‐Value Logic in Quantum Dot Cellular Automata

View full text Add to dashboard Cite

Analysis and design of a new fault‐tolerant digital comparator based on nano‐scale quantum technology

Jiao

2022

Concurrency and Computation

View full text Add to dashboard Cite

Summary Quantum‐dot cellular automata (QCA) is a transistor‐free technique for designing digital circuits. It is a substitute for CMOS technology for producing low‐energy and high‐speed digital circuits. In addition, the digital comparator is an important digital circuit; its fault‐tolerant design is examined in this article. Additionally, a coplanar QCA‐based fault‐tolerant comparator circuit with a small number of cells is suggested. The QCADesigner is used to achieve exact simulation results. The suggested fault‐tolerant comparator requires 63 QCA cells, uses 0.8 normalμ$$ \upmu $$m2, and has three clock cycles delay in accomplishing its purpose. Furthermore, simulation results demonstrate that the suggested comparator design with a limited number of cells can achieve a fault‐tolerant of 80% against cell missing, extra cell, cell displacement, and cell rotation faults.

show abstract

A novel fault tolerant majority gate in quantum-dot cellular automata to create a revolution in design of fault tolerant nanostructures, with physical verification

Cited by 44 publications

References 27 publications

A novel ultra‐dense and low‐power structure for fault‐tolerant three‐input majority gate in QCA technology

A novel ultra‐dense and low‐power structure for fault‐tolerant three‐input majority gate in QCA technology

References

Analysis and design of a new fault‐tolerant digital comparator based on nano‐scale quantum technology

Contact Info

Product

Resources

About