A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells

Abstract

Abstract-In this paper, we investigate the opportunity brought by controllable-polarity transistors to design efficient reconfigurable circuits. Controllable-polarity transistors are devices whose polarity can be electrostatically programmed to be either n-or p-type. Such devices are used to build ultrafine grain computation cells. These cells are arranged into regular matrices, called MClusters, with a fixed and incomplete interconnection pattern, employed to minimize the reconfigurable interconnection overhead. We subsequently use them into field-programmable gate arrays (FPGAs). To assess this architectural scheme in an efficient and objective manner, we present a complete benchmarking tool flow and focus on the packing algorithm developed to handle the architecture. We finally perform the evaluation with widely used benchmark circuits. Leveraging the ultrafine grain cells compactness from a system-level perspective, we show that FPGAs exploiting MClusters demonstrate average savings of 43% and 23% in area and delay, respectively, as compared with the CMOS lookup table FPGA counterpart at 22-nm technological node. IndexTerms-Controllable-polarity devices, fieldprogrammable gate arrays (FPGAs), packing tools, ultrafine grain logic, vertically stacked nanowires.

A review on embedded field programmable gate array architectures and configuration tools

“…• Mesh-based FPGAs, also called island-style FPGAs, are used in most academic and commercial SRAMbased FPGA architectures 2 [3][4][5][6]. In mesh-based FPGA architecture, LBs are placed in a 2D grid and surrounded by routing channels as illustrated in Figure 2.…”

Reconfigurable vertical field-effect transistor based on graphene/MoTe2/graphite heterostructure

“…These types of FETs are facing challenge in meeting the increasing demands for massive data processing. To overcome these challenges, reconfigurable FETs (RFETs) based on materials with ambipolar field-effect characteristics [1][2][3][4][5][6][7][8][9][10][11][12][13] that possess different operation modes and multiple functions, [14][15][16][17][18][19][20][21][22][23][24] were proposed as a promising solution to build multifunctional circuits with fewer compounds [16,[25][26][27][28]. Previously reported RFETs are based on a dual-gate planar structure [29][30][31].…”

Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support

“…In fact, the ratio of power dissipation, area density, and delay, from FPGA to application specific integrated circuit (ASIC), is respectively 7-14, 18-35, and 3-4 times [1]. This happens because a large part of the FPGA is dedicated to routing interconnect [2]. To make FPGAs more efficient, recent works investigated improvements of computer-aided design (CAD) algorithms used in each step of mapping a logic circuit into FPGAs.…”

“…FPGA designers can investigate two architectural factors: logic block granularity and routing interconnect topology. The first factor consists of exploring new logic block structures or exploring multigranularity architectures that can enhance FPGA functionality and performance [2]. The second factor consists of exploring new interconnect topologies.…”

“…The second factor consists of exploring new interconnect topologies. According to [2], FPGA routing architecture is more critical than logic architecture since it denotes 60% of the power dissipation, 80% of the area density, and 80% of the delay. Therefore, FPGA routing architecture is the bottleneck behind FPGA performance inefficiency and that is why we will tackle interconnect exploration in this paper.…”