A Novel Half-Adder Using Single Electron Tunneling Technology

Rehan, Sameh

doi:10.1109/nems.2007.352018

Cited by 13 publications

(3 citation statements)

References 8 publications

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“…An electron tunnels through the insulator if the distance between the conductors is small enough [5][6][7][8][9]. The theory of single electron phenomena shows that the charging energy is:…”

Section: Introductionmentioning

confidence: 99%

Area efficient digital logic NOT gate using single electron box (SEB)

Bahrepour

2017

Int. J. Simul. Multisci. Des. Optim.

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-The continuing scaling down of complementary metal oxide semiconductor (CMOS) has led researchers to build new devices with nano dimensions, whose behavior will be interpreted based on quantum mechanics. Singleelectron devices (SEDs) are promising candidates for future VLSI applications, due to their ultra small dimensions and lower power consumption. In most SED based digital logic designs, a single gate is introduced and its performance discussed. While in the SED based circuits the fan out of designed gate circuit should be considered and measured. In the other words, cascaded SED based designs must work properly so that the next stage(s) should be driven by the previous stage. In this paper, previously NOT gate based on single electron box (SEB) which is an important structure in SED technology, is reviewed in order to obtain correct operation in series connections. The correct operation of the NOT gate is investigated in a buffer circuit which uses two connected NOT gate in series. Then, for achieving better performance the designed buffer circuit is improved by the use of scaling process.

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Section: Introductionmentioning

confidence: 99%

Area efficient digital logic NOT gate using single electron box (SEB)

Bahrepour

2017

Int. J. Simul. Multisci. Des. Optim.

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“…The design of different SE logic gates are reported in [9][10][11][12]. The design of 2-bit decoders is presented in [13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

D3. Design and simulation of novel single-electron coding nano-circuits using room temperature summing-inverter gates

Yakout

Rehan

2012

2012 29th National Radio Science Conference (NRSC)

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The Single-Electron (SE) summing-inverter (SI) NOR and NAND gates are among the basic functional SE circuits. In this paper, the design of multi-input SE SI NOR and NAND gates are reviewed. Novel SE decimal-to-BCD encoders and binary decoders, which are composed of SI gates, are designed for all combinations of active inputs and outputs. The simulated designs work properly with only one voltage source of 500 mV for a wide range of temperatures (from 40K to 400K). The detailed schematic diagrams along with the corresponding SIMON 2 simulation results at room temperature (that include input and output signals as well as the stability diagrams) of the novel SE decimal-to-BCD encoders as well as the developed SE binary decoders are presented.

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“…technology, utilizing a variety of logic such as majority gate (MAJ), 6 7 threshold logic gate (TLG), 8 pass-transistor logic (PTL), 9 binary decision diagram (BDD), 10 and many others. [11][12][13][14] While these pure SED-based adders dramatically reduce circuit area and power dissipation, they can only work at extremely low temperature (less than 10 K) due to the crucial limitation of thermal effect, making them impractical for real applications. Several FAs using hybrid CMOS-SET architecture have also been reported recently with increased temperature operation (up to room temperature).…”

Section: Introductionmentioning

confidence: 99%

Hybrid CMOS-SET Arithmetic Circuit Design Using Coulomb Blockade Oscillation Characteristic

Deng¹,

Chen²

2011

Jnl of Comp & Theo Nano

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Hybrid CMOS-SET architectures, which combine the merits of CMOS and single electron transistor (SET) devices, promise to be a practical implementation for nanometer scale circuit design. In this work, we propose the design of two typical arithmetic circuits, namely adder and multiplier, using hybrid CMOS-SET architectures. For full adders (FAs) design, we present three different implementations based on multiple-valued logic (MVL), phase modulation and frequency modulation. These FAs fully utilize SET's unique characteristic of Coulomb blockade oscillation and exhibit improved performance in terms of circuit area/complexity, power dissipation and temperature effect. The structure based on frequency modulation also possesses high immunity against background charges, and is extended to design of multiple-bit adder and multiplier.

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A Novel Half-Adder Using Single Electron Tunneling Technology

Cited by 13 publications

References 8 publications

Area efficient digital logic NOT gate using single electron box (SEB)

Area efficient digital logic NOT gate using single electron box (SEB)

D3. Design and simulation of novel single-electron coding nano-circuits using room temperature summing-inverter gates

Hybrid CMOS-SET Arithmetic Circuit Design Using Coulomb Blockade Oscillation Characteristic

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