2010 International Conference on Reconfigurable Computing and FPGAs 2010
DOI: 10.1109/reconfig.2010.54
|View full text |Cite
|
Sign up to set email alerts
|

A Novel Hardware Implementation of the Compact Genetic Algorithm

Abstract: In this paper we show a novel and efficient design of a compact Genetic Algorithm (cGA) in Hardware. This design presents the following features: modularity, concurrency, minimal resource consumption, real time execution, and high scalability properties. According to the obtained results, we show that it is viable to have this search algorithm in Hardware to be used in real time applications. Keywords-Compact Genetic Algorithm; FPGA design2010 International Conference on Reconfigurable Computing 978-0-7695-431… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Year Published

2015
2015
2024
2024

Publication Types

Select...
3

Relationship

0
3

Authors

Journals

citations
Cited by 3 publications
(2 citation statements)
references
References 12 publications
0
2
0
Order By: Relevance
“…Other works employed cGA on various hardware devices [37,[233][234][235][236][237]. More recently, a GPU-enabled implementation of cGA was presented in [238], to solve a "seriously" large-scale (up to 10 million variables) Integer Linear Programming problem taken from [239], as well as continuous and discrete versions of the OneMax benchmark problem of up to one billion variables.…”
Section: Binary/discrete Compact Optimisation Algorithmsmentioning
confidence: 99%
“…Other works employed cGA on various hardware devices [37,[233][234][235][236][237]. More recently, a GPU-enabled implementation of cGA was presented in [238], to solve a "seriously" large-scale (up to 10 million variables) Integer Linear Programming problem taken from [239], as well as continuous and discrete versions of the OneMax benchmark problem of up to one billion variables.…”
Section: Binary/discrete Compact Optimisation Algorithmsmentioning
confidence: 99%
“…Furthermore, the simplicity and speed of altering programs related to the field programmable gate array (FPGA), besides decreasing implementation time, have solved a number of problems that are extra complex, computationally difficult, or very time consuming. Therefore, all these FPGA features along with the parallel asset of GAs make an attractive tool for GA hardware implementation, which can significantly reduce processing time and accelerate performance [16,[22][23][24]. In addition, the authors in [24] presented a GA simulation tool applicable in the context of an SDMA-OFDM system for determining an optimized solution.…”
Section: Introductionmentioning
confidence: 99%