A novel high-performance CMOS 1-bit full-adder cell

Shams, A.M.; Bayoumi, Magdy

doi:10.1109/82.842117

Cited by 157 publications

(64 citation statements)

References 9 publications

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“…The causes of dynamic power dissipation are due to switching power dissipation and short-circuit power dissipation when the logic level changes. Static power dissipations occurred due to diode leakage current [16]. In CMOS fixed power is quite small because of consideration of sub-micron technology.…”

Section: Methods and Mechanisms Of Power Ingestionmentioning

confidence: 99%

Low-Power High-Speed Double Gate 1-bit Full Adder Cell

Kumar¹,

Roy²,

Bhunia³

2016

International Journal of Electronics and Telecommunications

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Abstract-In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94µW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.Keywords-Low-power full-adder, Low-power CMOS design, multiplexer based full-adder design, multi-threshold voltage based Full-adder design, pass transmission logic.

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Section: Methods and Mechanisms Of Power Ingestionmentioning

confidence: 99%

Low-Power High-Speed Double Gate 1-bit Full Adder Cell

Kumar¹,

Roy²,

Bhunia³

2016

International Journal of Electronics and Telecommunications

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“…Related to the power consumption is the lowest supply voltage the design can still operate properly. Numerous full adder designs [1][2][3][4][5][6] in the categories of fully static CMOS, dynamic circuit, transmission gate, or pass transistor logic have been presented. The full adder design in fully static CMOS is the most conventional one but requires as many as 28 transistors.…”

mentioning

confidence: 99%

“…two additional transistors, the design was further improved in [3] and can eliminate the inverter from the critical path to avoid the possible short circuit power consumption for low power operation. In [4], a pass transistor based new Static Energy-Recovery Full (SERF) adder with as few as 10 transistors was presented.…”

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confidence: 99%

Comparative Analysis of 8-Bit Adder Cells Using CLRCL Full Adder Logic

Kumar¹,

Grover²,

Grover³

2014

GSTF J Comput

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Abstract-In this paper, we propose a modified low power 10-T Adder design usi ng 10 transist or s & 12 transist or s feat uring highe r computing speed, lower operating voltage, and lower energy consumption compared with peer designs. The simulation results, based on 0.18um process models, indicate that the proposed design has the lowest working Vdd and highest working frequency among all designs using 10 transistors & 12 transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases. Index Terms-Complementary & Level Restoring Full Adder, Boolean Logic I. INTRODUCTIONT he essence of the digital computing lies in the full adder design. The design criteria of a full adder are usually multifold. Transistor count is, of course, a primary concern which largely affects the design complexity of many function units such as multiplier and ALU. Two other important yet often conflicted design criteria are power consumption and speed. A better metric would be the power delay product or energy consumption per operation to indicate the optimal design tradeoffs. Related to the power consumption is the lowest supply voltage the design can still operate properly. Numerous full adder designs [1][2][3][4][5][6] in the categories of fully static CMOS, dynamic circuit, transmission gate, or pass transistor logic have been presented. The full adder design in fully static CMOS is the most conventional one but requires as many as 28 transistors. Dynamic circuits can significantly reduce the transistor count but the incurred power consumption, including that of the clock tree, is usually high. Building logic in transmission gate is another alternative to reduce the circuit complexity. In [1], transmission gate plus inverter based full adder designs were presented using 20 and 16 transistors, respectively. To pursue even lower transistor count full adder designs, pass transistor logic can be used in lieu of transmission gate. In [2], pass transistor logic based XOR/XNOR circuits were used and the full adder design consists of only 14 transistors. Despite the saving in transistor count, the output voltage level is degraded at certain input combinations due to threshold voltage loss problem. At the cost of

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“…Full adder for embedded applications using three inputs XOR have been reported [12]. A 16 transistor full adder cell with XOR/XNOR, pass transistors and transmission gate have been reported [13]. Structured approach for implementation of single bit full adders using XOR/XNOR has been reported [14] as shown in figure 1.…”

Section: Introductionmentioning

confidence: 99%