A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

Jiang, Jianwei; Zhu, Wenyi; Jun, Xiao; Zou, Shichang

doi:10.3390/electronics7100247

Cited by 11 publications

(6 citation statements)

References 19 publications

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“…One of the approaches to increase the tolerance of D-latches against DNU is to use larger transistors for sensitive nodes, but even under this solution, some nodes can be upset by large charge injection [11]. Other approaches resort to layout technology making use of well isolation or extending the node space and guard ring to help tolerate DNU [7].…”

Section: Introductionmentioning

confidence: 99%

Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

et al. 2023

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This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost profile. Thus, this D-latch may be useful for high reliability and high-performance safety-critical applications as it can detect and recover faults happening during holding time in harsh radiation environments. The proposed D-latch design is based on a low-cost single event double-node upset tolerant latch and a rule-based double-node upset (DNU) tolerant latch which provides it with the self-recoverability against DNU, but paired with a low transistor count and high performance. Simulation waveforms support the achievements and demonstrate that this new D-latch is fully self-recoverable against double-node upset. In addition, the minimum improvement of the delay-power-area product of the proposed rule-based design for the low-cost DNU tolerant self-recoverable latch (RB-LDNUR) is 59%, compared with the latest DNU self-recoverable latch on the literature.INDEX TERMS Delay-power-area product (DPAP), Double node upsets (DNU), High impedance state (HIS), Low cost single event double node upset tolerant (LSEDUT), Power-delay product (PDP), Single node upset (SNU), Soft error (SE).

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Section: Introductionmentioning

confidence: 99%

Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

et al. 2023

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“…Therefore, in order to provide highly reliable integrated circuits, it is necessary to design storage cells that can tolerate and even recover from MNU. To provide radiation hardening capability, researchers have proposed a series of radiation-hardened circuit structures [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Some of them use time redundancy, e.g., using delay elements as error-filterable components [8], some use pulse detection technology, such as that in [9], and some use space redundancy, e.g., introducing redundant storage nodes and/or triple-moduleredundancy (TMR) along with voting circuits [10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

“…To provide radiation hardening capability, researchers have proposed a series of radiation-hardened circuit structures [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Some of them use time redundancy, e.g., using delay elements as error-filterable components [8], some use pulse detection technology, such as that in [9], and some use space redundancy, e.g., introducing redundant storage nodes and/or triple-moduleredundancy (TMR) along with voting circuits [10][11][12][13][14]. In recent years, with the exploration of deep space, there are more and more cases of MNU, and the demand for a latch that can provide complete MNU self-recoverability is greatly increased [2,6].…”

Section: Introductionmentioning

confidence: 99%

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

Yan,

Zhou,

Wei

et al. 2023

2023 IEEE International Test Conference in Asia (ITC-Asia)

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As CMOS processes continue to shrink, nano-scale CMOS latches have become increasingly sensitive to multiplenode upset (MNU) errors caused by radiation. To tolerate MNU, a novel quadruple-node-upset (QNU) self-recoverable latch is proposed in this paper. The proposed latch is mainly constructed from six blocks of three-level C-elements (TLCEs) and six inverters. With the mutual feedback of the various TLCEs, the proposed latch can recover from any QNU. Furthermore, due to the clock gating methodology and a highspeed transmission path, the proposed latch has lower overhead in terms of power dissipation and transmission delay. Simulation results show that the proposed latch achieves high reliability with moderate overhead compared to typical existing latches.

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“…Traditional D-latches and memory cells are very vulnerable against upsets; thus, many approaches have been proposed to solve this problem; among these are hardened circuit design [8], error correcting codes (ECC) [9] and temporal redundancy [10]. Many new D-latches have also been proposed to increase immunity against SEU [11][12][13][14][15][16][17] and SET [7,13]. The design of these D-latches is based on filtering the SEU or/and SET.…”

Section: Introductionmentioning

confidence: 99%

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

et al. 2021

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In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

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A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

Cited by 11 publications

References 19 publications

Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

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