A Novel High Speed, Low Power, and Symmetrical Phase Frequency Detector with Zero Blind Zone and π Phase Difference Detection Ability

Ghasemi, Shima Tayyeb; Baradaranrezaeii, Ali

doi:10.1007/s00034-019-01312-w

Cited by 11 publications

(3 citation statements)

References 17 publications

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“…Second, the single cycle time of the low‐frequency signal is more extended than the high‐frequency signal; the pulses generated in each cycle are more, which can better restore the modulated signal. But it can also be seen from Figure 10B that this modulation method had more DC components, which can be eliminated by

π

type filter when the volume limit of the instrument is not high 27 …”

Section: The Design Of the Transmitter Circuitmentioning

confidence: 97%

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A portable frequency‐domain electromagnetic detection system

Peng,

Zhao,

Zhang

et al. 2024

Circuit Theory & Apps

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SummaryFrequency‐domain detection stands as a critical method in remote geophysical exploration; however, its practical application is constrained by the considerable size of the requisite instrumentation. In this paper, we present a compact frequency domain electromagnetic detection system. The integration of intelligent power devices and a novel hardware architecture substantially diminishes the system's dimensions, thereby enhancing its portability. Furthermore, the system design incorporates sinusoidal pulse width modulation and digital phase‐locked amplification to ensure the efficacy of the proposed system. Both the transmitter and receiver system are constrained to dimensions smaller than 1.5 m. Subsequent experimental validation attests to the exemplary hardware performance of the proposed system, with the transmitting voltage of the transmitter circuit attaining 500 V, and the receiver circuit exhibiting a sensitivity as low as 10−8 V. Significantly, this design paradigm not only facilitates the integration of transmitter and receiver systems for frequency‐domain electromagnetic detection but also introduces novel prospects for the application of frequency‐domain electromagnetic detection methods across diverse fields.

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π

type filter when the volume limit of the instrument is not high 27 …”

Section: The Design Of the Transmitter Circuitmentioning

confidence: 97%

“…But it can also be seen from Figure 10B that this modulation method had more DC components, which can be eliminated by π type filter when the volume limit of the instrument is not high. 27…”

Section: The Basic Performance Test Of the Transmitter Circuitmentioning

confidence: 99%

A portable frequency‐domain electromagnetic detection system

Peng,

Zhao,

Zhang

et al. 2024

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…The detection range is ± half the master clock period [19]. Standard cell flipflops (FFs) sample the time difference between the input and output clocks of the DCDL [16], [20], [21]. Since these signals can have an arbitrary time difference depending on the delay of the DCDL and jitter, there can occur setup-and-hold time violations in such FFs, which could lead to a metastable output.…”

Section: B Time Errors In the Pdmentioning

confidence: 99%

20-ps Resolution Clock Distribution Network for a Fast-Timing Single-Photon Detector

Egidos

Ballabriga

Bandi

et al. 2021

IEEE Trans. Nucl. Sci.

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The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The clock distribution network (CDN) that delivers the master clock signal must compensate process-voltage-temperature variations to reduce static time errors (skew) and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100-ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a selfregulated CDN that fulfills these requirements is presented for the FastICpix single-photon detector aiming at a 65-nm process. A 40-MHz master clock is distributed to 64 × 64 pixels over an area of 2.4 × 2.4 cm 2 using digital delay-locked loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution.

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Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application

Pradhan

Jana

2022

Circuits Syst Signal Process

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A Novel High Speed, Low Power, and Symmetrical Phase Frequency Detector with Zero Blind Zone and π Phase Difference Detection Ability

Cited by 11 publications

References 17 publications

A portable frequency‐domain electromagnetic detection system

A portable frequency‐domain electromagnetic detection system

20-ps Resolution Clock Distribution Network for a Fast-Timing Single-Photon Detector

Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application

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