A Novel instruction stream buffer for VLIW architectures

Chiu, Jih-Ching; Yang, Kaiming

doi:10.1016/j.compeleceng.2009.08.006

Cited by 4 publications

(2 citation statements)

References 14 publications

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“…Instruction compression technique makes the execute packet separate while it brings the advantages [3,4], as shown in Figure 1. The irregular length of the execute packet may exceed cache line boundaries, and be distributed in two consecutive cache line, which caused a non-alignment cache line.…”

Section: Intorductionmentioning

confidence: 99%

“…Thus the separated execute packet can not be simultaneously issued to the execution unit, which reduces the fetch and execute efficiency. The characteristics of the typical digital signal processing algorithms show small-scale loop program consumes the major execution time [4]. If the execute packet is frequently separated in the loop program, the consequent separated execute packet would greatly reduce the performance of the DSP Fetch pipeline.…”

Section: Intorductionmentioning

confidence: 99%

See 1 more Smart Citation

A Novel Two-Level Instruction Issue Window Based on VLIW Architecture

Yang¹,

Chen²,

Wu³

2011

AMR

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Instruction compression technique overcomes the drawbacks of traditional VLIW architectures with low density in the instruction cache. However, the separated long instruction word was arranged into two cache line. It comes to be a bottleneck problem for VLIW architecture processor performance because these split long instruction word can not be fetched and issued simultaneously. A novel two-level instruction issue window mechanism is proposed in this paper. It solves the instruction fetch and issue problem in separating instruction words. It provides more effective and continuous instruction flow, and stores one iteration of the loop body to support software pipeline technique, which improves VLIW DSP processor performance effectively. Proposed machanism was synthesized to evaluate its overall costs, and the performance speedup result for DSP/IMG library bencharks using the cycle accurate simulator are presented.

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Section: Intorductionmentioning

confidence: 99%

Section: Intorductionmentioning

confidence: 99%