A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes

Song, Suwen; Cui, Hangxuan; Tian, Jing; Lin, Jun; Wang, Zhongfeng

doi:10.1109/tcsii.2019.2938562

Cited by 3 publications

(5 citation statements)

References 10 publications

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“…The latest developed work belongs to Song et al [120]. They improved [119] by proposing a clipped-modified ISRB-MLGD algorithm, introducing two complexity-reduction modifications and an unsaturated clipping method, achieving higher performance with lower implementation complexity, raising the throughput to 136 Mbps.…”

Section: ) Ems Algorithmmentioning

confidence: 99%

“…Contrarily, works that do not report SNR but report a fixed number of iterations (without early termination) [68], [72]- [75], [79], [100], [101], [103], [104], [106], [109], [115], [120], [122], [123], [128], [132], can be compared with decoders in the same class (no SNR and fixed number of iterations) since throughput performance can be normalized by the number of iterations.…”

Section: ) Analysismentioning

confidence: 99%

“…In [8], [120], the authors do not report the code size but instead report the number of symbols, while in [122] they do not report code weights (d v , d c ). These setups do not allow researchers to understand the parallelization degree of the decoders.…”

Section: ) Analysismentioning

confidence: 99%

“…Of the surveyed papers, only [8], [68], [106]- [109], [116], [118], [120] report values for power. Power values help Fig.…”

Section: ) Analysismentioning

confidence: 99%

“…The designs using ISRB [120], IHRB [121] and WBRB [48] achieve excellent performance and can be alternatives to better-known algorithms such as MM and EMS. In this figure, we can see that data points can be clustered in process node technologies.…”

Section: Asicmentioning

confidence: 99%

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A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

Ferraz

Subramaniyan

Ramesh

et al. 2022

IEEE Commun. Surv. Tutorials

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Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and Manuscript

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Section: ) Ems Algorithmmentioning

confidence: 99%