A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization

Chen, Yuguang; Wen, Wan-Yu; Wang, Yunting; Lee, You-Luen; Chang, Shih-Chieh

doi:10.1109/aspdac.2016.7428019

Cited by 3 publications

(1 citation statement)

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“…Moreover, the toggling rate of the on-chip bus becomes one of the main design issues because it dominates the power consumption and degrades the performance due to a complex scalability [4,5]. For example, the existing on-chip buses, such as AHB [6] and AXI [7] from ARM Holdings, Wishbone from Silicore Corporation [8], and OCP from OCP-IP [9], cost much hardware resource in terms of slice/gate count and energy consumption, due to a large number of IO and signal definitions and complicated structures.…”

Section: Introductionmentioning

confidence: 99%

Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure

Yang

Andrian

2017

VLSI Design

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This paper proposes a novel bus encoding method on MBUS in order to reduce the power consumption of system-on-chips (SoCs). The main contribution is to lower the bus activity by an average 64.55% and thus decrease the IO power consumption through reconfiguring the MBUS transmission. This method is effective because field-programmable gate array (FPGA) IOs are most likely to have very large capacitance associated with them and consequently dissipate a lot of dynamic power. Experimental result shows an average 70.96% total power reduction compared with the original MBUS implementation.

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Section: Introductionmentioning

confidence: 99%