A Novel Low On−State Resistance Si/4H−SiC Heterojunction VDMOS with Electron Tunneling Layer Based on a Discussion of the Hetero−Transfer Mechanism

Abstract

In this study, we propose a novel silicon (Si)/silicon carbide (4H−SiC) heterojunction vertical double−diffused MOSFET with an electron tunneling layer (ETL) (HT−VDMOS), which improves the specific on−state resistance (RON), and examine the hetero−transfer mechanism by simulation. In this structure, the high channel mobility and high breakdown voltage (BV) are obtained simultaneously with the Si channel and the SiC drift region. The heavy doping ETL on the 4H−SiC side of the heterointerface leads to a low heterointerface resistance (RH), while the RH in H−VDMOS is extremely high due to the high heterointerface barrier. The higher carrier concentration of the 4H−SiC surface can significantly reduce the width of the heterointerface barrier, which is demonstrated by the comparison of the conductor energy bands of the proposed HT−VDMOS and the general Si/SiC heterojunction VDMOS (H−VDMOS), and the electron tunneling effect is significantly enhanced, leading to a higher tunneling current. As a result, a significantly improved trade−off between RON and BV is achieved. With similar BV values (approximately 1525V), the RON of the HT−VDMOS is 88% and 65.75% lower than that of H−VDMOS and the conventional SiC VDMOS, respectively.