A Novel Low Power Architecture for DLL-Based Frequency Synthesizers

Rahimpour

et al. 2013

Circuit Theory & Apps

Self Cite

SUMMARYLock time and convergence time are the most important challenges in delay-locked loops (DLLs). In this paper we cover French very high frequency band with a novel all-digital fast-lock DLL-based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22-27 delay cells, and f REF = 16 MHz, which can produce output frequency in range of 176-216 MHz. Locking time is approximately 0.3 μs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure.

Section: Simulation and Resultsmentioning

confidence: 86%

Section: Architecture Of Conventional Dllsmentioning

confidence: 99%

Section: Architecture Of Conventional Dllsmentioning

confidence: 99%

“…Analog structure for delay‐locked loop‐based frequency synthesizers to generate fractional multiples of reference frequency .…”

Section: Conventional Dll‐based Frequency Synthesizer For Covering Vhmentioning

confidence: 99%

See 2 more Smart Citations

A new fast‐lock, low‐jitter, and all‐digital frequency synthesizer for DVB‐T receivers

Rahimpour

et al. 2013

Circuit Theory & Apps

Self Cite

“…The proposed dual PFD DLL is designed in TSMC 0.18um CMOS Technology in frequency near to 167MHz (T REF =6ns) by using ADS (Advanced Design System) simulator. All building blocks of DLLs are implemented by CML logic as in [12]. Figure 6 shows the results of simulation of the proposed dual PFD delay locked loop.…”

Section: Simulations and Resultsmentioning

confidence: 99%

Dual Phase Detector Based Delay Locked Loop for High Speed Applications

2014

IJE

In this paper a new architecture for delay locked loops is proposed. Static phase offset and reset path delay are the most important problems in phase-frequency detectors (PFD). The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and output of the DLL. Near locking, an XOR gate is used to act as a PFD which makes the DLL locks with less jitter. Also, the reset path time and glitch are decreased by using the XOR gate. The proposed architecture has been designed in TSMC 0.18um CMOS Technology. The simulation results support the theoretical design aspects.

Analysis and design of a low jitter delay‐locked loop using lock state detector

Modanlou

2021

Circuit Theory & Apps

Self Cite

Summary In this paper, a technique is proposed to improve the jitter performance of a delay‐locked loop (DLL). The DLL is structured by charge pump (CP), phase detector (PD), voltage control delay line (VCDL) and the reference clock. The jitter generated by each part of DLL is separately studied, and a closed‐form equation is extracted. This closed‐form equation shows that the jitter generated by CP, PD and the secondary jitter of the reference clock and VCDL is applied to output by the control voltage. A jitter improving circuit is used to cancel the jitter of the control voltage. To verify the closed‐form equation, the DLL is designed in 0.18 μm CMOS technology with the proposed technique to improve the output jitter. The simulated root‐mean‐square and peak‐to‐peak jitters are 2.12 and 4.37 ps at 250 MHz, respectively. The power dissipation at 250 MHz is 2.78 mW for a supply voltage of 1.2 V.