A novel low power Exclusive-OR via cell level-based design function in quantum cellular automata

Berarzadeh, Mohammad; Mohammadyan, Somaye; Navi, Keivan; Bagherzadeh, Nader

doi:10.1007/s10825-017-0986-7

Cited by 26 publications

(12 citation statements)

References 25 publications

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“…e estimation is performed at temperature T � 2 K by employing three channeling energy levels, namely, 0.5E k , 1.0E k , and 1.5E k . As is shown in Figure 9, our proposed gate has the lowest energy dissipation value at three separate tunneling energy levels as compared with the circuits in [22,23,25,27,32]. Consequently, the use of the proposed XOR gate in the design of parity generator circuits will provide more power savings.…”

Section: Simulation Results and Comparisonmentioning

confidence: 93%

“…Previous QCA Exclusive-OR Circuits. Up to date, a widespread study in QCA has been outlined to achieve exclusive-OR designs [22][23][24][25][26][27] which are used in many of the digital logic circuits such as error detection circuits, arithmetic logic circuits, multiplexers, full adders, and comparators. e XOR gate is composed of two inputs and one output.…”

Section: Related Workmentioning

confidence: 99%

“…It plays an important role in the design of digital circuits. As a result, several attempts have been done to implement this important logic component, especially in the QCA technology [22,23,25,27]. In this section, we propose a novel QCA circuit for the parity generator.…”

Section: Parity Generator Designsmentioning

confidence: 99%

“…In this focus, we demonstrate only the QCA layouts of 4-and 8 -bit parity generator circuits because of the lack of space. Here, the cell count, area, and delay of the designed 4-and 8 -bit parity generator circuits are considerably improved compared to 4-and 8 bit parity generator circuits in [22,23,25].…”

Section: Parity Generator Designsmentioning

confidence: 99%

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An Ultra-Low Power Parity Generator Circuit Based on QCA Technology

Gassoumi

Touil

Ouni

et al. 2019

Journal of Electrical and Computer Engineering

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Quantum-dot cellular automata (QCA) technology is one of the emerging technologies that can be used for replacing CMOS technology. It has attracted significant attention in the recent years due to its extremely low power dissipation, high operating frequency, and a small size. In this study, we demonstrate an n-bit parity generator circuit by utilizing QCA technology. Here, a novel XOR gate is used in the synthesis of the proposed circuit. The proposed gate is based on electrostatic interactions between cells to perform the desired function. The comparison results demonstrate that the designed QCA circuits have advantages compared to other circuits in terms of cell count, area, delay, and power consumption. The QCADesigner software, as widely used QCA circuit design and verification, has been used to implement and to verify all of the designs in this study. Power dissipation has been computed for the proposed circuit using accurate QCAPro power estimator tool.

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Section: Simulation Results and Comparisonmentioning

confidence: 93%

Section: Related Workmentioning

confidence: 99%

Section: Parity Generator Designsmentioning

confidence: 99%

Section: Parity Generator Designsmentioning

confidence: 99%

See 2 more Smart Citations

An Ultra-Low Power Parity Generator Circuit Based on QCA Technology

Gassoumi

Touil

Ouni

et al. 2019

Journal of Electrical and Computer Engineering

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“…QCA, as one of the solutions, is a revolutionary hopeful transistor less quantum paradigm with ultra-low power consumption and highly small feature size [10][11][12][13]. QCA logic states are introduced by a cell that is applied to encode and transfer data by the two state electron configurations [14][15][16][17]. A QCA cell group can be integrated and ordered specially in order to conduct calculational functions [18][19][20].…”

Section: Introductionmentioning

confidence: 99%

An effective nano design of demultiplexer architecture based on coplanar quantum‐dot cellular automata

Afrooz

Navimipour

2021

IET Circuits, Devices & Syst

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Quantum‐dot cellular automata (QCA) are prospective nanotechnology with striking performance to tackle the shortcomings of complementary metal‐oxide‐semiconductor (CMOS) transistor‐based technology such as fabrication dimensions and switching speed. The demultiplexer, as a crucial component for the design of many logic circuits, comprises a circuit for separating the multiplex data into the component data. The demultiplexer is highly utilised in the communication system for building serial data lines to parallel ones. So, its efficient schematisation has turned to an issue that has captured the concentration of the investigation group. Therefore, a novel structure of QCA‐based one to two demultiplexers is proposed, and it is employed to design one to four demultiplexers. QCAdesigner software, as a powerful layout and tool for simulation, is utilised for evaluating the validity and practicality of the proposed structures. The detailed evaluation of proposed layouts shows excellent performance than prior operations, and notable developments regarding the occupied area, cell count, and latency.

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