A novel low power keeper technique for pseudo domino logic

Bansal, Deepika; Singh, B. P.; Kumar, Ajay

doi:10.1109/conecct.2015.7383865

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Pseudo Domino Logic Using Precharge Keeper Circuit1

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2017

2022

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Cited by 4 publications

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“…In the evaluation phase, the precharge keeper transistor P PK is turned on and the dynamic node F is charged fully to VDD according to the input values as depicted in Figure 6. The precharge keeper technique resolves the charge sharing problem of the standard keeper circuit [12].…”

Section: Pseudo Domino Logic Using Precharge Keeper Circuitmentioning

confidence: 99%

Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic

Bansal¹,

Singh²,

Kumar³

2017

Bulletin EEI

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The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.

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Section: Pseudo Domino Logic Using Precharge Keeper Circuitmentioning

confidence: 99%