A novel low temperature integration of hybrid CMOS devices on flexible substrates

Gowrisanker, S.; Quevedo‐Lopez, Manuel; Alshareef, Husam N.; Gnade, Bruce E.; Venugopal, Sameer M.; Krishna, R.; Kaftanoglu, Korhan; Allee, David R.

doi:10.1016/j.orgel.2009.06.012

Cited by 29 publications

(15 citation statements)

References 27 publications

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“…Furthermore, the maximum processing temperature is maintained below 100°C, which is compatible with flexible substrates used in flexible electronic applications. 32 Normally, in devices with SiO 2 as the gate dielectric, the mobility increases linearly with increasing charge per unit area on the semiconductor side of the insulator ͑Q S ͒ and the gate field ͑E͒ until it eventually saturates. Because Q S is a function of the concentration of accumulated carriers in the channel region ͑N͒ and the accumulation region is confined very close to the interface of the insulator with the organic semiconductor, 33 an increase in gate voltage ͑V G ͒ results in an increase in E and N. Dimitrakopoulos and Malenfant demonstrated that high mobilities in pentacene TFTs can be achieved at low operating voltages when relatively high dielectric constant gate insulator materials are used.…”

mentioning

confidence: 99%

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

Salas-Villasenor

Mejía

Hovarth

et al. 2010

Electrochem. Solid-State Lett.

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mentioning

confidence: 99%

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

Salas-Villasenor

Mejía

Hovarth

et al. 2010

Electrochem. Solid-State Lett.

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“…Using a process previously reported by our group [41][42][43], bottom contact devices are fabricated on silicon nitride (Si 3 N 4 ) deposited on silicon wafers. Chromium (50 nm) was deposited by e-beam evaporation and then lithographically patterned and wet etched to form the gate electrode.…”

Section: Methodsmentioning

confidence: 99%

“…The performance of the resulting devices was evaluated and the DC electrical characteristics of the pentacene TFTs were measured in the air using a Keithley 4200 semiconductor characterization system. The detail discussion of the fabrication and measurement conditions of the transistors is given in [41][42][43].…”

Section: Methodsmentioning

confidence: 99%

Impact of semiconductor/metal interfaces on contact resistance and operating speed of organic thin film transistors

et al. 2010

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The contact resistance of field effect transistors based on pentacene and parylene has been investigated by experimental and numerical analysis. The device simulation was performed using finite element two-dimensional driftdiffusion simulation taking into account field-dependent mobility, interface/bulk trap states and fixed charge density at the organic/insulator interface. The width-normalized contact resistance extracted from simulation which included an interface dipole layer between the gold source/drain electrodes and pentacene was 91 k cm. However, contact resistance extracted from the simulation, without consideration of interface dipole was 52.4 k cm, which is about half of the experimentally extracted 108 k cm. This indicates that interface dipoles are critical effects which degrade performances of organic field effect transistors by increasing the contact resistance. Using numerical calculations and circuit simulations, we have predicted a 1 MHz switching frequency for a 1 µm channel length transistor without dipole interface between gold and pentacene. The transistor with dipole interface is predicted, via the same methods, to exhibit an operating frequency of less than 0.5 MHz.

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“…Using a process previously reported by our group [23,24], bottom contact devices are fabricated on silicon nitride (Si 3 N 4 ) deposited on silicon wafers. Chromium (50 nm) was deposited by e-beam evaporation and then lithographically patterned and wet etched to form the gate electrode.…”

Section: Pentacene Tftmentioning

confidence: 99%

CdS Thin Film Transistor for Inverter and Operational Amplifier Circuit Applications

Wondmagegn

Mejía

Salas-Villasenor

et al. 2016

Microelectronic Engineering

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Organic and inorganic thin film transistors (TFTs) are fabricated, simulated, and tested for circuit applications. The devices are based on polycrystalline cadmium sulfide (CdS) and pentacene thin films. Both devices are simulated and analyzed using two-dimensional finite element simulation methodology. For CdS, grain boundary and uniform trap distribution approaches are implemented. It is assumed that traps due to grain boundaries are uniformly distributed throughout the film. For pentacene a Poole-Frenkel mobility model is employed. After matching device simulation with experimental data, the SPICE model parameters are extracted for circuit simulation. The devices are tested for both analog and digital circuits. operational amplifier (OPAMP) and inverter circuits are tested. Two OPAMP topologies are compared and the results are discussed. One of the topologies is based on all n-type transistors using CdS TFT and the other topology is the two-stage Miller compensated CMOS design based on CdS and pentacene TFTs. The operational amplifiers have an open-loop voltage gain of 25.9 dB and 29.7 dB respectively. The performance of the CMOS design is found to be limited by performance of pentacene transistor.

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A novel low temperature integration of hybrid CMOS devices on flexible substrates

Cited by 29 publications

References 27 publications

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

Impact of semiconductor/metal interfaces on contact resistance and operating speed of organic thin film transistors

CdS Thin Film Transistor for Inverter and Operational Amplifier Circuit Applications

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