A Novel LTPS-TFT Pixel Circuit to Compensate the Electronic Degradation for Active-Matrix Organic Light-Emitting Diode Displays

Fan, Chih‐Peng; Tseng, Fan-Ping; Lai, Hui-Lung; Sun, Bo-Jhang; Chao, Kuang-Chi; Chen, Yi-Chiung

doi:10.1155/2013/839301

Cited by 4 publications

(3 citation statements)

References 18 publications

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“…The backplane technology of low-temperature poly-Si (LTPS) thin-film transistors (TFTs) are widely used in pixel circuits for portable AMOLED displays, since it has excellent current capability [5][6][7]. However, it has some demerits, such as nonuniformity of threshold voltage (V TH ) and high manufacturing costs [8,9].…”

Section: Introductionmentioning

confidence: 99%

New Low-Frame-Rate Compensating Pixel Circuit Based on Low-Temperature Poly-Si and Oxide TFTs for High-Pixel-Density Portable AMOLED Displays

2021

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A new low-frame-rate active-matrix organic light-emitting diode (AMOLED) pixel circuit with low-temperature poly-Si and oxide (LTPO) thin-film transistors (TFTs) for portable displays with high pixel density is reported. The proposed pixel circuit has the excellent ability to compensate for the threshold voltage variation of the driving TFT (ΔVTH_DTFT). By the results of simulation based on a fabricated LTPS TFT and a-IZTO TFT, we found that the error rates of the OLED current were all lower than 2.71% over the range of input data voltages when ΔVTH_DTFT = ±0.33 V, and a low frame rate of 1 Hz could be achieved with no flicker phenomenon. Moreover, with only one capacitor and two signal lines in the pixel circuit, a high pixel density and narrow bezel are expected to be realized. We revealed that the proposed 7T1C pixel circuit with low driving voltage and low frame rate is suitable for portable displays.

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Section: Introductionmentioning

confidence: 99%

New Low-Frame-Rate Compensating Pixel Circuit Based on Low-Temperature Poly-Si and Oxide TFTs for High-Pixel-Density Portable AMOLED Displays

2021

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“…For these transitions to translate into viable commercial products, achieving uniformity of electrical characteristics over a large area will be critical in ensuring high yield alongside superior electrical performance. Polysilicon circuits are prime candidates as the platform of choice for many of these applications, based on technology maturity, as well as performance resulting from high charge carrier mobility 17 – 28 . However, the polycrystalline nature of the material induces device-to-device variability due to the arbitrary number and position of grain boundaries in the transistor channel.…”

Section: Introductionmentioning

confidence: 99%

“…This deleterious effect may be more pronounced when the material is purposely engineered for very high carrier mobility via large grains; the presence of a grain boundary in a transistor’s active region results in a significant lowering of the effective mobility, and of drain current. Mitigating strategies for compensating the effects of random grain boundary positions include current-mode driving schemes or compensation circuitry 17 , 29 – 33 . These solutions increase design time, power consumption, and circuit complexity, affecting yield and application viability.…”

Section: Introductionmentioning

confidence: 99%

Towards manufacturing high uniformity polysilicon circuits through TFT contact barrier engineering

Sporea

Wheeler

Stolojan

et al. 2018

Sci Rep

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The predicted 50 billion devices connected to the Internet of Things by 2020 has renewed interest in polysilicon technology for high performance new sensing and control circuits, in addition to traditional display usage. Yet, the polycrystalline nature of the material presents significant challenges when used in transistors with strongly scaled channel lengths due to non-uniformity in device performance. For these new applications to materialize as viable products, uniform electrical characteristics on large areas will be essential. Here, we report on the effect of deliberately engineered potential barrier at the source of polysilicon thin-film transistors, yielding highly-uniform on-current (<8% device-to-device, accounting for material, as well as substantial geometrical, variations). The contact-controlled architecture of these transistors significantly reduces kink effect and produces high intrinsic gain over a wide range of drain voltage (2–20 V). TCAD simulations associate critical grain boundary position and the two current injection mechanisms in this type of device, showing that, for the geometry considered, the most unfavorable location is ~150 nm inside the source area. At this point, grain boundary contributes to increasing the resistance of the source pinch-off region, reducing the current injection from the bulk of the source area. Nevertheless, the effect is marginal, and the probability of a grain boundary existing at this position is low. This new understanding is instrumental in the design of new signal conversion and gain circuits for flexible and low-power sensors, without the need for complex compensation methods.

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P‐2: A Novel Method for LTPS Model Extraction with Hysteresis and Transient Current Analysis

Kuo

Tsai

Tseng

et al. 2015

Symp Digest of Tech Papers

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Time-sampling measurements are used in this paper to build time dependent LTPS TFT current model. The device model that considers bias and time dependent threshold voltage (V th ) shift and mobility degradation is implemented in Eldo through GUDM for simulating a pixel circuit as an indicator of panel performance. Author Keywordstime-sampling measurement, LTPS, V th shift, mobility degradation, Eldo, GUDM, transient current. Objective and BackgroundThe performance of a low-temperature poly-silicon (LTPS) thin film transistor (TFT) is usually judged by its threshold voltage (V th ), mobility (), sub-threshold swing (SS) and on-off current ratio (I on /I off ) [1] . In addition to the trap concentration, the activation energy of the traps should be noticed too [11]. Nonetheless, the activation energy of the traps is bias dependent [11]. Therefore, the factors for threshold voltage shift include the gate and drain bias can be expressed as ∆V th = ∆V th (V gs , V ds , Time, Temp). Our goal is to extract the time and bias dependency factor of V th shift from I d -V g and time sampling measure method. The objective of building this model is to enable designers to simulate the image retention time in AMOLED pixel circuit for panel performance estimation. ResultsA P-type LTPS TFT is fabricated with 120nm gate insulator layer and channel dimension of 30μm in length and 3 μm wide. The electrical characteristics were measured in ambient temperature (25℃).When studying the image retention behavior, the chessboard pattern shown in Figure 1 is usually used to observe the image residual phenomenon which is the direct evidence of image retention and the criterion of the panels' quality check. The panel is controlled to display chessboard image for a certain length of time and then switch to pure gray image to observe how long the residual images of previous chessboard image remains. For the pixels, the image change consists of two types of operations, which are white (L255) to gray (L128) and black (L0) to gray (L128). Two panels with different image retention time are selected as the target for examining the effectiveness of the proposed model extraction method. One of them has residual image that lasts 10 seconds, and that of the other lasts 120 seconds. On each panel, one TEG is selected to represent the I-V characteristics of all TFT in the panel. In the following paragraphs, the origins of the residual image will be analyzed and an analytical approach of deriving and extracting the model parameters with transient current will be presented. For an AMOLED panel, the luminance is from the OLED device whose current is controlled by the driving TFT. Therefore, we will focus on the variations of the LTPS TFT because the behavior variations of OLED are within milliseconds and is far from the scale of retention time observed [12]. To mimic the stability of the driving TFT current on a

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A Novel LTPS-TFT Pixel Circuit to Compensate the Electronic Degradation for Active-Matrix Organic Light-Emitting Diode Displays

Cited by 4 publications

References 18 publications

New Low-Frame-Rate Compensating Pixel Circuit Based on Low-Temperature Poly-Si and Oxide TFTs for High-Pixel-Density Portable AMOLED Displays

New Low-Frame-Rate Compensating Pixel Circuit Based on Low-Temperature Poly-Si and Oxide TFTs for High-Pixel-Density Portable AMOLED Displays

Towards manufacturing high uniformity polysilicon circuits through TFT contact barrier engineering

P‐2: A Novel Method for LTPS Model Extraction with Hysteresis and Transient Current Analysis

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